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2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)最新文献

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A Highly Efficient 0.2 THz Varactor-Less VCO with -7 dBm Output Power in 130nm SiGe 一种高效的0.2 THz无变容压控振荡器，输出功率为-7 dBm，尺寸为130nm
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340100
Pei-Yuan Chiang, O. Momeni, P. Heydari
{"title":"A Highly Efficient 0.2 THz Varactor-Less VCO with -7 dBm Output Power in 130nm SiGe","authors":"Pei-Yuan Chiang, O. Momeni, P. Heydari","doi":"10.1109/CSICS.2012.6340100","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340100","url":null,"abstract":"A highly efficient voltage controlled oscillator (VCO) with a new varactor-less-based frequency-tuning topology for terahertz (THz) frequencies is presented. The tuning technique is based on a variable inductance seen at the emitter node of a base degenerated transistor. Fabricated in a 130nm SiGe BiCMOS process, the VCO achieves a tuning range of 3.5% and output power of -7.25 dBm at 201.5GHz. The VCO consumes 30mW of DC power, resulting in a record-breaking power efficiency of 0.6%. To demonstrate the functionality of the tuning technique, three other VCO prototypes at different oscillation frequencies, including one operating at 222.7~229 GHz range, have been implemented.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126565112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
DARPA's Microscale Power Conversion Program DARPA的微型功率转换项目
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340120
J. Albrecht, A. Kane, Tsu-Hsi Chang
{"title":"DARPA's Microscale Power Conversion Program","authors":"J. Albrecht, A. Kane, Tsu-Hsi Chang","doi":"10.1109/CSICS.2012.6340120","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340120","url":null,"abstract":"Starting more than a decade ago, DARPA began funding the materials and device developments of group III-nitride electronics to push toward the limits of cutoff frequency, breakdown voltage, power density and reliability of GaN HEMTs. These transistors have the potential to realize RF power amplifiers with both high output power and power added-efficiency (PAE), compared with those based on other III-V materials (GaAs or InP). Device properties notwithstanding, GaN-based, transmitting high Peak-to-Average Ratio (PAR) RF signals will result in lower PAE when constrained to fixed drain voltage during input back-off. The Microscale Power Conversion (MPC) program seeks to create a very high efficiency RF transmitter as either a monolithic integrated circuit or system-in-package module in which a MMIC power amplifier is integrated (co-designed) with a dynamic voltage power supply and control circuit. The key enabling device technology to be developed for the high-speed power supply modulator is a fast, low-loss GaN power switch. Track 1 of the MPC program seeks to develop packaged, high-speed (>;1 GHz), E-mode power switches capable of simultaneously satisfying 50 volt operation, 10 W power handling, Blocking voltage >; 200 volts, dynamic on-resistance Ron-dynamic <; 1 Ω-mm and output voltage slew rate >; 500 V/ns. The final goal of the MPC program (Track 2) is to leverage the power switch developments in Track 1 to realize co-designed RF transmitters. These RF transmitters will operate at X-band frequencies (or higher) while providing 5 W of RF output power at an average composite PAE of 75%, with at least 500 MHz of RF envelope bandwidth.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132755119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Optoelectronic Chip Based on a Laser Integrated with a Thermoelectrophotonic Heat Pump 基于激光与热电泳热泵集成的光电子芯片
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340117
X. Liu, G. Zhao, Y. Zhang, D. Deppe
{"title":"Optoelectronic Chip Based on a Laser Integrated with a Thermoelectrophotonic Heat Pump","authors":"X. Liu, G. Zhao, Y. Zhang, D. Deppe","doi":"10.1109/CSICS.2012.6340117","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340117","url":null,"abstract":"Data are presented demonstrating, to our knowledge, the first monolithic chip integrating a semiconductor laser with a spontaneous light emitting diode optical pump that can also act as a heat pump. The light emitting diode operates in the voltage bias regime needed to generate a thermoelectrophotonic heat absorption. Under ideal operation the light emitting diode can efficiently optically pump the semiconductor laser, while at the same time absorbing heat generated by the laser and electrical contacting to the chip.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129306841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Modeling of FET Switches FET开关的建模
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340092
F. Kharabi
{"title":"Modeling of FET Switches","authors":"F. Kharabi","doi":"10.1109/CSICS.2012.6340092","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340092","url":null,"abstract":"This paper describes the salient features of modeling FET devices for switch applications, with examples in GaAs PHEMT and GaN HEMT technologies. It explains the subtle differences that differentiate these models from PA models and what is required to accurately describe their small- and large- signal behavior. In that respect, suggestions are made on how to approach formulation of critical parameters in meeting unique requirements of modeling high-power switches with novel device structures.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115751558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Surface-Potential-Based Compact Model for Study of Non-Linearities in AlGaAs/GaAs HEMTs 基于表面电位的紧凑模型研究AlGaAs/GaAs hemt的非线性
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340055
S. Khandelwal, T. Fjeldly
{"title":"A Surface-Potential-Based Compact Model for Study of Non-Linearities in AlGaAs/GaAs HEMTs","authors":"S. Khandelwal, T. Fjeldly","doi":"10.1109/CSICS.2012.6340055","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340055","url":null,"abstract":"We present a continuous surface-potential- based electro-thermal compact model suitable for the study of intermodulation distortion IMD in GaAs HEMT devices. We have developed a precise analytical calculation for the position of the Fermi level Ef in these devices from a consistent solution of Schrödinger's and Poisson's equations. The accuracy of our calculation is of the order of pico-volts. Ef is used to define the surface-potential ψ and subsequently derive the drain current Id. We use the developed Id model for prediction of IMD in these devices using Volterra series method. The model is in excellent agreement with experimental IMD data. The impact of various real device effects like self- heating, mobility degradation etc., on the non- linear behavior of the device is analyzed using the model.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122703663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Dual-Output Stacked Class-EE Power Amplifiers in 45nm SOI CMOS for Q-Band Applications 用于q波段应用的45nm SOI CMOS双输出堆叠ee类功率放大器
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340107
A. Chakrabarti, J. Sharma, H. Krishnaswamy
{"title":"Dual-Output Stacked Class-EE Power Amplifiers in 45nm SOI CMOS for Q-Band Applications","authors":"A. Chakrabarti, J. Sharma, H. Krishnaswamy","doi":"10.1109/CSICS.2012.6340107","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340107","url":null,"abstract":"Stacking multiple devices improves the output power and efficiency in mmWave power amplifiers by increasing the achievable output voltage swing. This work presents a new topology for stacked Class-E-like power amplifiers. In this technique, a Class-E load network is placed at the drain node of each stacked device, which imparts a true Class-E behavior to all the devices in the stack. The resulting topology is called the Dual (Multi) Output Stacked Class-EE PA. Two Q-band prototypes - a unit cell with 2 devices stacked, and a power-combined version employing two such unit cells - have been fabricated in IBM's 45nm SOI CMOS technology using the 56nm body-contacted devices. Measurements yield a peak PAE of 25.5% for the Dual Output Stacked Class-EE unit cell with saturated output power of 17.9 dBm, and a peak PAE >;16% for the power-combined version with saturated output power >;19.1 dBm. Excellent correspondence is observed between simulation and measurement as a consequence of active and passive device modeling efforts.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127144407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Back to the Future: An All-NMOS SiC Linear Voltage Regulator for High Temperature Applications 回到未来:用于高温应用的全nmos SiC线性稳压器
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340080
J. Valle-Mayorga, A. Rahman, H. Mantooth
{"title":"Back to the Future: An All-NMOS SiC Linear Voltage Regulator for High Temperature Applications","authors":"J. Valle-Mayorga, A. Rahman, H. Mantooth","doi":"10.1109/CSICS.2012.6340080","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340080","url":null,"abstract":"The first power management option in integrated SiC is presented in this paper. This linear voltage regulator consists of an error amplifier and a W/L=32,000 depletion NMOS as the pass device. The feedback and frequency compensation networks are external. Due to the developing nature of SiC processes, the voltage reference used for the error amplifier is external as well. This SiC linear voltage regulator was fabricated in a 4H-SiC, all NMOS, 2 μm process and can operate at temperatures up to 225°C. The voltage regulator can regulate at voltages between 10 and 15 V up to a maximum load current of 2 A with less than 4% load regulation and 192 mV/V line regulation at 225°C. This regulator sets the reference for future SiC linear regulators, and as the manufacturing processes for SiC mature, better load and line regulations will be achievable and yet over a wider temperature range and higher output voltages than standard silicon.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125904142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Engineering Design of a near Junction Thermal Transport Heat Spreader 近结热输运散热器的工程设计
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340097
G. Mandrusiak, S. Weaver, D. Lin, E. Browne, R. Vetury, M. Aimi, O. Boomhower
{"title":"Engineering Design of a near Junction Thermal Transport Heat Spreader","authors":"G. Mandrusiak, S. Weaver, D. Lin, E. Browne, R. Vetury, M. Aimi, O. Boomhower","doi":"10.1109/CSICS.2012.6340097","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340097","url":null,"abstract":"This paper describes a convection-based, self-contained heat spreader that provides device-level thermal management for GaN power amplifiers. The concept connects microchannels etched into the backside of the die to a liquid flow circuit that includes autonomous flow-balancing valves, a diaphragm pump, and a high-performance heat exchanger. The integrated system provides a heat spreading capability that reduces transistor gate heat fluxes by up to four orders of magnitude, enabling device-level temperature control using conventional cold plates. This paper will review the analysis used to design the key components in the assembly and to project their performance as part of an integrated system.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125955411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Compact Integration of Sub-Harmonic Resistive Mixer with Differential Double Slot Antenna in G-Band Using 50nm InP-HEMT MMIC Process 采用50nm InP-HEMT MMIC工艺实现g波段差分双槽天线亚谐波阻性混频器的紧凑集成
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340081
Y. Karandikar, H. Zirath, Yu Yan, V. Vassilev
{"title":"Compact Integration of Sub-Harmonic Resistive Mixer with Differential Double Slot Antenna in G-Band Using 50nm InP-HEMT MMIC Process","authors":"Y. Karandikar, H. Zirath, Yu Yan, V. Vassilev","doi":"10.1109/CSICS.2012.6340081","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340081","url":null,"abstract":"Sub-Harmonic resistive HEMT based mixers in Gband have been designed and integrated with Double Slot Antenna in Differential Configuration for the first time. This novel topology shows compact integration of active devices between antenna ports while achieving 25 GHz bandwidth around 200 GHz. The dual-gate 50nm x 15um InP HEMT used in the design achieves the conversion loss of 15 dB with +3 dBm LO power drive. Furthermore, a similar topology when used as a Harmonic mixer using a single gate device offers 16.5 dB conversion loss for +4 dBm LO power. For compact integration, via hole matching on slot antenna is also presented.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114674166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
High Performance Ka-Band VPIN Limiters 高性能ka波段VPIN限制器
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340108
R. Santhakumar, D. Allen
{"title":"High Performance Ka-Band VPIN Limiters","authors":"R. Santhakumar, D. Allen","doi":"10.1109/CSICS.2012.6340108","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340108","url":null,"abstract":"The purpose of this paper is to demonstrate the successful design of passive high power multi-stage limiters operating from 33 to 36 GHz using a high-yielding GaAs Vertical PIN diode process. Measured CW data shows that a two stage design achieves less than 0.5 dB insertion loss while achieving a flat leakage of about 21 dBm. A three stage design achieves 0.8 dB small signal insertion loss and 19 dBm flat leakage. A key to achieving the performance was the accurate large signal modeling of the PIN diodes.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127077600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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