{"title":"高性能ka波段VPIN限制器","authors":"R. Santhakumar, D. Allen","doi":"10.1109/CSICS.2012.6340108","DOIUrl":null,"url":null,"abstract":"The purpose of this paper is to demonstrate the successful design of passive high power multi-stage limiters operating from 33 to 36 GHz using a high-yielding GaAs Vertical PIN diode process. Measured CW data shows that a two stage design achieves less than 0.5 dB insertion loss while achieving a flat leakage of about 21 dBm. A three stage design achieves 0.8 dB small signal insertion loss and 19 dBm flat leakage. A key to achieving the performance was the accurate large signal modeling of the PIN diodes.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"High Performance Ka-Band VPIN Limiters\",\"authors\":\"R. Santhakumar, D. Allen\",\"doi\":\"10.1109/CSICS.2012.6340108\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The purpose of this paper is to demonstrate the successful design of passive high power multi-stage limiters operating from 33 to 36 GHz using a high-yielding GaAs Vertical PIN diode process. Measured CW data shows that a two stage design achieves less than 0.5 dB insertion loss while achieving a flat leakage of about 21 dBm. A three stage design achieves 0.8 dB small signal insertion loss and 19 dBm flat leakage. A key to achieving the performance was the accurate large signal modeling of the PIN diodes.\",\"PeriodicalId\":290079,\"journal\":{\"name\":\"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"volume\":\"75 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-10-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSICS.2012.6340108\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2012.6340108","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The purpose of this paper is to demonstrate the successful design of passive high power multi-stage limiters operating from 33 to 36 GHz using a high-yielding GaAs Vertical PIN diode process. Measured CW data shows that a two stage design achieves less than 0.5 dB insertion loss while achieving a flat leakage of about 21 dBm. A three stage design achieves 0.8 dB small signal insertion loss and 19 dBm flat leakage. A key to achieving the performance was the accurate large signal modeling of the PIN diodes.
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