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2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)最新文献

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Methods for virtual junction temperature measurement respecting internal semiconductor processes 半导体内部制程的虚结温度测量方法
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-06-15 DOI: 10.1109/ISPSD.2015.7123455
C. Herold, J. Franke, Riteshkumar Bhojani, A. Schleicher, J. Lutz
{"title":"Methods for virtual junction temperature measurement respecting internal semiconductor processes","authors":"C. Herold, J. Franke, Riteshkumar Bhojani, A. Schleicher, J. Lutz","doi":"10.1109/ISPSD.2015.7123455","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123455","url":null,"abstract":"This paper discusses the limitation in measurement accuracy of junction temperature measurements of bipolar devices. A limiting factor the measurement delay, caused by slow removal of charge carriers, was investigated by single pulse measurements and evaluated by simulations. A minimal measurement delay of 650μs was found for a 6.5 kV IGBT at high temperature.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116899866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Automatic layout optimization of DMOS transistors for lower peak temperatures and increased energy capability DMOS晶体管的自动布局优化，以降低峰值温度和提高能量能力
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123421
T. Zawischka, M. Pfost
{"title":"Automatic layout optimization of DMOS transistors for lower peak temperatures and increased energy capability","authors":"T. Zawischka, M. Pfost","doi":"10.1109/ISPSD.2015.7123421","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123421","url":null,"abstract":"DMOS transistors often suffer from substantial self-heating during high power dissipation, which can lead to thermal destruction if the device temperature reaches excessive values. A successfully demonstrated method to reduce the peak temperature is the redistribution of power dissipation density from the hotter to the cooler device areas by careful layout modification. However, this is very tedious and time-consuming if complex-shaped devices as often found in industrial applications are considered. This paper presents an approach for fully automatic layout optimization which requires only a few hours processing time. The approach is applied to complex-shaped test structures which are investigated by measurements and electro-thermal simulations. Results show a significantly lower peak temperature and an energy capability gain of 84%, offering potential for a 18 % size reduction of active area.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"304 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122382102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-voltage full-SiC power module: Device fabrication, testing and high frequency application in kW-level converter 高压全sic功率模块:器件制造、测试及在kw级变换器中的高频应用
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123437
Sizhe Chen, Junwei He, Kuang Sheng
{"title":"High-voltage full-SiC power module: Device fabrication, testing and high frequency application in kW-level converter","authors":"Sizhe Chen, Junwei He, Kuang Sheng","doi":"10.1109/ISPSD.2015.7123437","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123437","url":null,"abstract":"In this work, we introduce a high-voltage, full-SiC power module based on SiC junction field effect transistors (JFETs) and schottky barrier diodes (SBDs). The process development and fabrication of 4kV SiC JFETs and SBDs are first introduced and a 3500V/15A full-SiC power module which is fabricated with self-fabricated devices is presented. The power module is also evaluated in a high frequency boost converter and demonstrates that it is capable of working at a frequency up to 100kHz and a DC voltage of 1500V. Both turn-on and turn-off times are less than 150ns. A high converter efficiency of 97% is obtained at 50kHz switching frequency and it drops to 95% at 100kHz. This work shows that SiC JFET power module is capable of high frequency and high efficiency applications in the medium voltage range.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129526584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Conductivity modulated on-axis 4H-SiC 10+ kV PiN diodes 电导率调制轴上4H-SiC 10+ kV PiN二极管
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123441
Arash Salemi, H. Elahipanah, B. Buono, A. Hallén, J. Hassan, P. Bergman, G. Malm, C. Zetterling, M. Ostling
{"title":"Conductivity modulated on-axis 4H-SiC 10+ kV PiN diodes","authors":"Arash Salemi, H. Elahipanah, B. Buono, A. Hallén, J. Hassan, P. Bergman, G. Malm, C. Zetterling, M. Ostling","doi":"10.1109/ISPSD.2015.7123441","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123441","url":null,"abstract":"Degradation-free ultrahigh-voltage (>10 kV) PiN diodes using on-axis 4H-SiC with low forward voltage drop (V<sub>F</sub> = 3.3 V at 100 A/cm<sup>2</sup>) and low differential on-resistance (R<sub>ON</sub> = 3.4 mΩ.cm<sup>2</sup>) are fabricated, measured, and analyzed by device simulation. The devices show stable on-state characteristics over a broad temperature range up to 300 °C. They show no breakdown up to 10 kV, i.e., the highest blocking capability for 4H-SiC devices using on-axis to date. The minority carrier lifetime (τ<sub>P</sub>) is measured after epitaxial growth by time resolved photoluminescence (TRPL) technique at room temperature. The τ<sub>P</sub> is measured again after device fabrication by open circuit voltage decay (OCVD) up to 500 K.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124699221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Numerical study of GaN-on-Si HEMT breakdown instability accounting for substrate and packaging interactions 考虑衬底和封装相互作用的GaN-on-Si HEMT击穿不稳定性的数值研究
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123469
F. Monti, I. Imperiale, S. Reggiani, E. Gnani, A. Gnudi, G. Baccarani, L. Nguyen, A. Hernandez-Luna, J. Huckabee, N. Tipirneni, M. Denison
{"title":"Numerical study of GaN-on-Si HEMT breakdown instability accounting for substrate and packaging interactions","authors":"F. Monti, I. Imperiale, S. Reggiani, E. Gnani, A. Gnudi, G. Baccarani, L. Nguyen, A. Hernandez-Luna, J. Huckabee, N. Tipirneni, M. Denison","doi":"10.1109/ISPSD.2015.7123469","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123469","url":null,"abstract":"The electron and hole impact-ionization coefficients in AlxGa1-xN have been calibrated through a Chynoweth law by using a Monte Carlo theoretical study and experimental data at different ambient temperatures. The model has been used to investigate the breakdown characteristics in AlGaN/GaN HEMTs. The concurrent effect of charge trapping in the GaN buffer and impact-ionization generation in the device failure mechanism has been studied by simulating the off-state breakdown under a dc stress. The sensitivity of the AlGaN/GaN HEMT to parasitic charging in molding compound has been investigated by incorporating the passivation and encapsulation layers in the TCAD setup and implementing the conductivity losses in the mold compound at high temperature.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124715196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
60 GHz wireless signal transmitting gate driver for IGBT 用于IGBT的60 GHz无线信号发射门驱动器
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123407
Kenichi Yamamoto, F. Ichihara, K. Hasegawa, Masanori Tukuda, I. Omura
{"title":"60 GHz wireless signal transmitting gate driver for IGBT","authors":"Kenichi Yamamoto, F. Ichihara, K. Hasegawa, Masanori Tukuda, I. Omura","doi":"10.1109/ISPSD.2015.7123407","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123407","url":null,"abstract":"This paper shows the very first demonstration result of wireless IGBT gate drive using with 60 GHz wireless module with sufficient “real-time” control with 100 ns-level time delay with small fluctuation of the delay.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114776654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Predictive and efficient modeling of hot-carrier degradation in nLDMOS devices nLDMOS器件热载流子退化的预测和有效建模
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123471
P. Sharma, S. Tyaginov, Y. Wimmer, F. Rudolf, K. Rupp, M. Bina, H. Enichlmair, Jong-Mun Park, H. Ceric, T. Grasser
{"title":"Predictive and efficient modeling of hot-carrier degradation in nLDMOS devices","authors":"P. Sharma, S. Tyaginov, Y. Wimmer, F. Rudolf, K. Rupp, M. Bina, H. Enichlmair, Jong-Mun Park, H. Ceric, T. Grasser","doi":"10.1109/ISPSD.2015.7123471","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123471","url":null,"abstract":"We present a physical model for hot-carrier degradation (HCD) which is based on the information provided by the carrier energy distribution function. In the first version of our model the distribution function is obtained as the exact solution of the Boltzmann transport equation, while in the second one we employ the simplified drift-diffusion scheme. Both versions of the model are validated against experimental HCD data in nLDMOS transistors, namely against the change of such device characteristics as the linear and saturation drain currents. We also compare the intermediate results of these two versions, i.e. the distribution function, defect generation rates, and interface state density profiles. Finally, we make a conclusion on the vitality of the drift-diffusion based version of the model.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133614887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Next generation 650V CSTBTTM with improved SOA fabricated by an advanced thin wafer technology 下一代650V CSTBTTM采用先进的薄晶片技术制造，具有改进的SOA
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123381
R. Kamibaba, Kazuya Konishi, Y. Fukada, A. Narazaki, M. Tarutani
{"title":"Next generation 650V CSTBTTM with improved SOA fabricated by an advanced thin wafer technology","authors":"R. Kamibaba, Kazuya Konishi, Y. Fukada, A. Narazaki, M. Tarutani","doi":"10.1109/ISPSD.2015.7123381","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123381","url":null,"abstract":"Using an advanced thin wafer technology, we have successfully fabricated the next generation 650V class IGBT with an improved SOA and maintaining the narrow distribution of the electrical characteristics for industrial applications. The applied techniques were the finer pattern transistor cell, the thin wafer process and the optimized back side doping concentration profiles. With the well organized back-side wafer process, the practically large chip has achieved without any sacrifice of the production yield. As a results, VCEsat-Eoff trade-off relationship and an Energy of Short Circuit by active Area (ESC/A) are improved in comparison with the conventional Punch Through (PT) structure.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127838205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
95% DC-DC conversion efficiency by novel trench power MOSFET with dual channel structure to cut body diode losses 采用新型沟槽功率MOSFET双沟道结构，实现95%的DC-DC转换效率，降低体二极管损耗
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123390
O. Haberlen, M. Polzl, J. Schoiswohl, M. Rosch, S. Léomant, G. Nobauer, W. Rieger
{"title":"95% DC-DC conversion efficiency by novel trench power MOSFET with dual channel structure to cut body diode losses","authors":"O. Haberlen, M. Polzl, J. Schoiswohl, M. Rosch, S. Léomant, G. Nobauer, W. Rieger","doi":"10.1109/ISPSD.2015.7123390","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123390","url":null,"abstract":"A novel 25V silicon trench power MOSFET optimized for fast and high efficient switching with record Ron*Qg and Ron*Qoss figure-of-merits is reported. A dual channel structure with two different gate oxide thicknesses allows reducing the body diode conduction losses by up to 50% and enables 95% DC-DC conversion efficiency.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124389138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Suppression of switching loss dependence on charge imbalance of superjunction MOSFET 超结MOSFET电荷不平衡对开关损耗的抑制
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123475
Hiroaki Yamashita, Hideyuki Ura, S. Ono, M. Nashiki, Kenji Mii, W. Saito, J. Onodera, Y. Hokomoto
{"title":"Suppression of switching loss dependence on charge imbalance of superjunction MOSFET","authors":"Hiroaki Yamashita, Hideyuki Ura, S. Ono, M. Nashiki, Kenji Mii, W. Saito, J. Onodera, Y. Hokomoto","doi":"10.1109/ISPSD.2015.7123475","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123475","url":null,"abstract":"We discuss switching behavior of superjunction (SJ)-MOSFETs in terms of interaction between MOS gate structure and charge imbalance (CIB) of SJ structure. Resistive load switching behavior of SJ-MOSFET was analyzed by device simulation. CIB changes the gate voltage transient behavior between gate threshold voltage and gate plateau voltage via modification of the potential near the gate. We found key parameter which determines the effect of MOS structure and layout upon loss, and indicated robust MOS gate design and layout from the perspective of switching loss. Finally, we confirmed the conclusion by experiment.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115008914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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