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2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)最新文献

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A monolithic SiC drive circuit for SiC Power BJTs 用于SiC功率BJTs的单片SiC驱动电路
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123445
Saleh Kargarrazi, L. Lanni, A. Rusu, C. Zetterling
{"title":"A monolithic SiC drive circuit for SiC Power BJTs","authors":"Saleh Kargarrazi, L. Lanni, A. Rusu, C. Zetterling","doi":"10.1109/ISPSD.2015.7123445","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123445","url":null,"abstract":"Silicon Carbide (SiC) is an excellent candidate for high temperature electronics applications, thanks to its wide bandgap. SiC power BJTs are commercially available nowadays, and it is demanding to drive them efficiently. This paper reports on the design, layout specifics, and measurements results of a SiC drive integrated circuit (IC) designed for driving SiC power BJTs. The circuit has been tested in different loading conditions (resistive and capacitive), at switching frequencies up to 500kHz, and together with a commercial power BJT. The SiC drive IC is shown to have a robust operation over the entire temperature range from 25 °C to 500 °C.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131048189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Design and optimization of GaN lateral polarization-doped super-junction (LPSJ): An analytical study GaN横向极化掺杂超结(LPSJ)的设计与优化:分析研究
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123442
B. Song, M. Zhu, Zongyang Hu, K. Nomoto, D. Jena, H. Xing
{"title":"Design and optimization of GaN lateral polarization-doped super-junction (LPSJ): An analytical study","authors":"B. Song, M. Zhu, Zongyang Hu, K. Nomoto, D. Jena, H. Xing","doi":"10.1109/ISPSD.2015.7123442","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123442","url":null,"abstract":"A 2D analytical model for breakdown voltage (BV) and specific on-resistance (Ron, sp) of GaN lateral polarization-doped super-junction (LPSJ) devices has been developed. The electric field along the critical path has been modeled and compared with 2D simulation results, followed by breakdown voltage calculation using impact ionization integral. Design space and optimization of LPSJ has been disused in terms of n/p pillar doping, thickness and aluminum composition xAl in grading AlGaN. The 2D analytical model represents a more realistic performance limit than the 1D model and the Ron, sp of LPSJ with xAl = 0.3 shows > 10x reduction over conventional GaN junctions for BV>2 kV. It can provide useful guidelines for the development of LPSJ and the design criteria to achieve minimum Ron, sp.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132877554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The effect of the collector contact design on the performance and yield of 800V Lateral IGBTs for power ICs 集电极触点设计对功率集成电路用800V横向igbt性能和良率的影响
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123419
G. Camuso, F. Udrea, N. Udugampola, V. Pathirana, T. Trajkovic
{"title":"The effect of the collector contact design on the performance and yield of 800V Lateral IGBTs for power ICs","authors":"G. Camuso, F. Udrea, N. Udugampola, V. Pathirana, T. Trajkovic","doi":"10.1109/ISPSD.2015.7123419","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123419","url":null,"abstract":"We report here a new physical phenomenon related to contact etch depth in High Voltage Lateral IGBTs (LIGBTs) and propose a design technique to increase yield of LIGBTs in high volume production. We prove for the first time that the contact geometry and placement have direct effect on Collector injection efficiency in LIGBTs. An improved design for 800V LIGBTs obtained by optimising the layout of contact openings is proposed. The new structure resulted in 15% increase in production yield.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123046960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
1.7kV high-power IGBT fabrication by bonded-wafer-concept 结合晶圆概念制造1.7kV大功率IGBT
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123476
S. Matthias, W. Janisch, C. Papadopoulos, A. Kopta
{"title":"1.7kV high-power IGBT fabrication by bonded-wafer-concept","authors":"S. Matthias, W. Janisch, C. Papadopoulos, A. Kopta","doi":"10.1109/ISPSD.2015.7123476","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123476","url":null,"abstract":"Lower losses and higher performance levels at elevated junction temperatures require fabrication processes enabling full design-flexibility for the IGBT buffer and anode to meet application requirements for the ≤1.7kV voltage-range. Here we present the bonded wafer concept that is enabling high thermal stability and soft and high turn-off capability due to full design flexibility for the critical backside layers.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125274828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling spatial and energy oxide trap distribution responsible for NBTI in p-channel power U-MOSFETs 模拟p沟道功率u - mosfet中NBTI的空间和能量氧化阱分布
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123412
A. Tallarico, E. Sangiorgi, C. Fiegna, P. Magnone, G. Barletta, A. Magri
{"title":"Modeling spatial and energy oxide trap distribution responsible for NBTI in p-channel power U-MOSFETs","authors":"A. Tallarico, E. Sangiorgi, C. Fiegna, P. Magnone, G. Barletta, A. Magri","doi":"10.1109/ISPSD.2015.7123412","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123412","url":null,"abstract":"In this paper, we present a combined measurement/simulation method, implemented in order to estimate the spatial and energy oxide trap distribution induced by negative bias temperature instability (NBTI) stress in p-channel power U-MOSFETs. The methodology consists in analyzing the recovery phase at different bias conditions and correlating the results with TCAD numerical simulations. We found an oxide trap distribution positioned between 2.24 and 3.04 nm distant from oxide/channel interface with an energy level confined in the silicon bandgap.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122618035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Multi-dimensional trade-off considerations of the 750V micro pattern trench IGBT for electric drive train applications 用于电力传动系统的750V微模式沟槽IGBT的多维权衡考虑
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123400
F. Wolter, W. Roesner, M. Cotorogea, T. Geinzer, M. Seider-Schmidt, Kae-Horng Wang
{"title":"Multi-dimensional trade-off considerations of the 750V micro pattern trench IGBT for electric drive train applications","authors":"F. Wolter, W. Roesner, M. Cotorogea, T. Geinzer, M. Seider-Schmidt, Kae-Horng Wang","doi":"10.1109/ISPSD.2015.7123400","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123400","url":null,"abstract":"The EDT2 750V uses a micro pattern trench cell with a narrow mesa for reducing the on-state losses with a tailored channel width for short circuit robustness. To account for high system stray inductances (Lstray) and currents for Full or Hybrid Electric Vehicle inverter applications, it features a 750V voltage rating compared to the predecessor IGBT3 650V by an optimized vertical structure and proper plasma shaping. This plasma distribution not only determines the performance tradeoff between on-state and switching losses, but at the same time defines the surge voltage for a given Lstray*I in the application as visualized in a switch-off loss vs. surge voltage trade-off diagram. Shaping of the feedback capacitance Cgc optimizes the tunability of the switching slopes by means of an external gate resistor for an easier adaption to a wider range of system inductances with low losses.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130305328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A RESURF P-N bimodal LDMOS suitable for high voltage power switching applications 一种适用于高压电源开关应用的RESURF P-N双峰LDMOS
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123389
Yongxi Zhang, S. Pendharkar, P. Hower, Salvatore Giombanco, Antonio Amoroso, F. Marino
{"title":"A RESURF P-N bimodal LDMOS suitable for high voltage power switching applications","authors":"Yongxi Zhang, S. Pendharkar, P. Hower, Salvatore Giombanco, Antonio Amoroso, F. Marino","doi":"10.1109/ISPSD.2015.7123389","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123389","url":null,"abstract":"A novel, high voltage, dual-gate lateral double diffusion MOSFET (LDMOS) with both p-type and n-type conduction is experimentally demonstrated using reduced surface field (RESURF) Si bulk technology. The p-n bimodal LDMOS can enhance drain saturation current by at least 30% with limited cost penalty compared to traditional n-LDMOS. Detailed analysis on the bimodal conduction LDMOS operation and DC output and temperature characteristics is presented. A simplified driving scheme is proposed to drive the dual-gate, p-n bimodal conduction LDMOS.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114337152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Ultra low miller capacitance trench-gate IGBT with the split gate structure 采用分栅结构的超低米勒电容沟栅IGBT
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123380
K. Ohi, Y. Ikura, A. Yoshimoto, K. Sugimura, Y. Onozawa, H. Takahashi, M. Otsuki
{"title":"Ultra low miller capacitance trench-gate IGBT with the split gate structure","authors":"K. Ohi, Y. Ikura, A. Yoshimoto, K. Sugimura, Y. Onozawa, H. Takahashi, M. Otsuki","doi":"10.1109/ISPSD.2015.7123380","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123380","url":null,"abstract":"This paper presents a newly developed trench gate IGBT which utilizes the split gate structure. It can realize both low Miller capacitance and high Injection Enhancement (IE) effect. The Miller capacitance has been reduced to 1/10 compared to that of the general trench gate structure with floating p-base. As a result, the turn-on power dissipation has been reduced by about 10% under the same turn-on di/dt and high recovery dV/dt controllability has also been achieved because of its lower gate-collector coupling. The trade-off relationship between the on-state voltage drop and the turn-off power dissipation has been improved by about 15% compared to the conventional IGBT.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117072586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A 0.18μm SOI BCD technology for automotive application 汽车用0.18μm SOI BCD技术
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123418
Y. Hao, P. C. Sim, B. Toner, M. Frank, M. Ackermann, A. Tan, U. Kuniss, E. Kho, J. Doblaski, E. Hee, M. Liew, A. Hoelke, S. Wada, T. Oshima
{"title":"A 0.18μm SOI BCD technology for automotive application","authors":"Y. Hao, P. C. Sim, B. Toner, M. Frank, M. Ackermann, A. Tan, U. Kuniss, E. Kho, J. Doblaski, E. Hee, M. Liew, A. Hoelke, S. Wada, T. Oshima","doi":"10.1109/ISPSD.2015.7123418","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123418","url":null,"abstract":"This paper presents a new SOI BCD technology at the 0.18μm node to fulfill the requirements for smart power IC technology targeted for automotive application. Built on a 1.8V and 5.0V CMOS core, there are 40V and 60V rated N/Pch MOS, with 25mΩ.mm2 RonA/57V BVdss having been achieved for the 40V NMOS with excellent process stability. Depletion NMOS, LV&HV diodes, 5V zener diode, high gain BJT, excellent matching well resistor, capacitors, top thick Copper Metallization option, embedded memory (OTP, CEEPROM, etc.) are also offered on this comprehensive technology platform.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123208267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
On-chip optical pumping of deep traps in AlGaN/GaN-on-Si power HEMTs AlGaN/GaN-on-Si功率hemt中深阱的片上光泵浦
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123424
Xi Tang, Baikui Li, K. J. Chen
{"title":"On-chip optical pumping of deep traps in AlGaN/GaN-on-Si power HEMTs","authors":"Xi Tang, Baikui Li, K. J. Chen","doi":"10.1109/ISPSD.2015.7123424","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123424","url":null,"abstract":"In this work, by using an on-chip Schottky-on-heterojunction light-emitting diode (SoH-LED) which is seamlessly integrated with the AlGaN/GaN high electron mobility transistor (HEMT), we studied the effect of on-chip light illumination on the de-trapping processes of electrons from both surface and bulk traps. Surface trapping was generated by applying OFF-state drain bias stress, while bulk trapping was generated by applying positive substrate bias stress. The de-trapping processes of surface and/or bulk traps were monitored by measuring the recovery of dynamic on-resistance Ron and/or threshold voltage Vth of the HEMT. The results show that the recovery processes of both dynamic Ron and threshold voltage Vth of the HEMT can be accelerated by the on-chip SoH-LED light illumination, demonstrating the feasibility of fully integrated opto-HEMTs to minimize the influences of traps during the dynamic operation of AlGaN/GaN power HEMTs.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124817638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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