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2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)最新文献

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A capacitive-loaded level shift circuit for improving the noise immunity of high voltage gate drive IC 一种提高高压栅极驱动集成电路抗噪声能力的容性负载电平移位电路
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123417
Yunwu Zhang, Jing Zhu, Weifeng Sun, Yangyang Lu, Lihui Gu, Sen Zhang, Wei Su
{"title":"A capacitive-loaded level shift circuit for improving the noise immunity of high voltage gate drive IC","authors":"Yunwu Zhang, Jing Zhu, Weifeng Sun, Yangyang Lu, Lihui Gu, Sen Zhang, Wei Su","doi":"10.1109/ISPSD.2015.7123417","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123417","url":null,"abstract":"A high voltage gate drive IC achieving the high dVS/dt noise immunity up to 85V/ns and the allowable negative VS swing to -12V at 15V supply voltage is proposed for the first time. The robust features are due to the presented capacitive loaded level shift circuit used in the gate driver. Measured and simulated results are performed to verify the electrical characteristics of the designed gate driver which is implemented in a 0.5um 600V Bipolar-CMOS-DMOS (BCD) technology.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134065179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Characteristics of 4H-SiC P-i-N diodes on lightly doped free-standing substrates 轻掺杂独立衬底上4H-SiC P-i-N二极管的特性
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123462
S. Chowdhury, C. Hitchcock, R. Dahal, I. Bhat, T. Chow
{"title":"Characteristics of 4H-SiC P-i-N diodes on lightly doped free-standing substrates","authors":"S. Chowdhury, C. Hitchcock, R. Dahal, I. Bhat, T. Chow","doi":"10.1109/ISPSD.2015.7123462","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123462","url":null,"abstract":"This paper presents static and dynamic electrical characteristics of implanted 4H-SiC PiN diodes fabricated on Si-face and C-face of lightly doped free-standing substrates. The device performance is found to be comparable to conventional diodes. Carrier lifetime of about 2.5 μs was measured for the drift region.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129542562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High voltage Si/SiC hybrid switch: An ideal next step for SiC 高压 Si/SiC 混合开关：碳化硅的理想下一步
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123446
Xiaoqing Song, A. Huang, Meng-Chia Lee, Chang Peng
{"title":"High voltage Si/SiC hybrid switch: An ideal next step for SiC","authors":"Xiaoqing Song, A. Huang, Meng-Chia Lee, Chang Peng","doi":"10.1109/ISPSD.2015.7123446","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123446","url":null,"abstract":"Silicon carbide (SiC) power switches such as MOSFET or JFET have demonstrated their superior advantages over silicon (Si) power devices such as IGBT, especially in terms of significantly reduced switching losses. A major issue facing large scale adoption of SiC power devices is still the much higher cost. This paper proposes that Si/SiC hybrid switch should be a natural next step moving forward for high voltage applications to address the cost issue. In the proposed Si/SiC hybrid switch, a SiC MOSFET is connected in parallel with Si IGBT to combine the advantages of IGBT and MOSFET. This concept can also works well with SiC JFET. A 6.5 kV Si IGBT and SiC MOSFET hybrid switch is developed as an example to demonstrate its superior cost/performance. The switching loss can be reduced by more than 70% at a cost of only 50% higher compared to Si IGBT. This work is especially essential for high voltage applications such as medium voltage motor drive, FACTS and HVDC systems.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128305774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Temperature dependence of single-event burnout for super junction MOSFET 超级结MOSFET单事件烧断的温度依赖性
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123397
Shunsuke Katoh, Eiji Shimada, Takayuki Yoshihira, Akihiro Oyama, S. Ono, Hideyuki Ura, Gentaro Ookura, W. Saito, Y. Kawaguchi
{"title":"Temperature dependence of single-event burnout for super junction MOSFET","authors":"Shunsuke Katoh, Eiji Shimada, Takayuki Yoshihira, Akihiro Oyama, S. Ono, Hideyuki Ura, Gentaro Ookura, W. Saito, Y. Kawaguchi","doi":"10.1109/ISPSD.2015.7123397","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123397","url":null,"abstract":"Single-Event Burnout (SEB) is one of the catastrophic failure effects that could cause destruction of a MOSFET. In the present work, we experimentally obtained the dependence of SEB tolerance of Super-junction (SJ) MOSFET on temperature and studied the mechanism of the dependence of SEB failure rate on temperature by simulation.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130674975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Current enhancement by conductivity modulation in diamond JFETs for next generation low-loss power devices 下一代低损耗功率器件中金刚石jfet电导率调制的电流增强
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123393
T. Iwasaki, H. Kato, J. Yaita, T. Makino, M. Ogura, D. Takeuchi, H. Okushi, S. Yamasaki, M. Hatano
{"title":"Current enhancement by conductivity modulation in diamond JFETs for next generation low-loss power devices","authors":"T. Iwasaki, H. Kato, J. Yaita, T. Makino, M. Ogura, D. Takeuchi, H. Okushi, S. Yamasaki, M. Hatano","doi":"10.1109/ISPSD.2015.7123393","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123393","url":null,"abstract":"Diamond junction field-effect transistors (JFETs) were operated in bipolar-mode to enhance the drain current. In unipolar-mode, the drain current in diamond JFET is limited by low activation of boron acceptors in the p-type channel. To increase the drain current, minority carriers were injected from the n+-diamond gates to p-channel, resulting in conductivity modulation. The drain current increased by a factor of up to 8.5 with current gains of 100-2600. We confirmed that the bipolarmode operation can be performed at a high temperature of 200 oC. The combination of the bipolar-mode and high temperature operation will lead to the realization of low-loss diamond power devices.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133564482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Enhancement-mode GaN-on-Si MOS-FET using Au-free Si process and its operation in PFC system with high-efficiency 采用无金硅工艺的增强型GaN-on-Si MOS-FET及其在PFC系统中的高效运行
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123426
H. Miyamoto, Y. Okamoto, H. Kawaguchi, Y. Miura, M. Nakamura, T. Nakayama, I. Masumoto, S. Miyake, T. Hirai, M. Fujita, Takehiro Ueda, K. Yamanoguchi, A. Tsuboi
{"title":"Enhancement-mode GaN-on-Si MOS-FET using Au-free Si process and its operation in PFC system with high-efficiency","authors":"H. Miyamoto, Y. Okamoto, H. Kawaguchi, Y. Miura, M. Nakamura, T. Nakayama, I. Masumoto, S. Miyake, T. Hirai, M. Fujita, Takehiro Ueda, K. Yamanoguchi, A. Tsuboi","doi":"10.1109/ISPSD.2015.7123426","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123426","url":null,"abstract":"We have developed an enhancement-mode GaN-on-Si MOS-FET with a thin GaN channel (40nm) on a thick AlGaN back barrier layer (1um), using Au-free 150-mm Si process. The developed device showed a threshold voltage Vt of 1.1 V, an on-resistance Ron of 5.4 mΩcm2 and a breakdown voltage BV of 730 V. The developed E-mode GaN MOS-FETs demonstrated the potential for compact and efficient power electronics. A Power Factor Correction (PFC) circuit using the packaged GaN device (20A, 650V) operated with high efficiency of > 94 % at Pout=300 W, Vout=390 V and fSW=300 kHz.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115413017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
High voltage thick SOI-LIGBT with high current density and latch-up immunity 高电压厚soi - light具有高电流密度和锁存抗扰度
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123416
Jing Zhu, Weifeng Sun, Long Zhang, Yicheng Du, Hui Yu, Keqin Huang, Yan Gu, Sen Zhang, Wei Su
{"title":"High voltage thick SOI-LIGBT with high current density and latch-up immunity","authors":"Jing Zhu, Weifeng Sun, Long Zhang, Yicheng Du, Hui Yu, Keqin Huang, Yan Gu, Sen Zhang, Wei Su","doi":"10.1109/ISPSD.2015.7123416","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123416","url":null,"abstract":"A high voltage SOI-LIGBT with high current capability and latch-up immunity is proposed in this paper. The proposed SOI-LIGBT features the segmented U-shaped N<sup>+</sup> emitter and the `JFET'-region is surrounded by the U-shaped channel. The U-shaped channel significantly enhances the electron injection from the emitter to the N-drift region, which leads to an improvement on the current density. Meanwhile, the P<sup>+</sup> emitter between the adjacent U-shaped N<sup>+</sup> emitters forms an additional hole current path, which is beneficial to the latch-up immunity. The experiments demonstrate that the proposed SOI-LIGBT exhibits a high current density (J<sub>C</sub>) of 240A/cm<sup>2</sup> at V<sub>CE</sub> = 3V and V<sub>GE</sub> = 5V, a low specific on-resistance (R<sub>on.sp</sub>) of 1.25Ω·mm<sup>2</sup> with breakdown voltage (BV) of 590V. The saturation current is about 550A/cm<sup>2</sup> at V<sub>CE</sub> = 500V without latch-up issue.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115810584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A 10kV/200A SiC MOSFET module with series-parallel hybrid connection of 1200V/50A dies 一种10kV/200A SiC MOSFET模块，采用1200V/50A芯片串并联混合连接
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123461
Q. Xiao, Yang Yan, Xinke Wu, Na Ren, Kuang Sheng
{"title":"A 10kV/200A SiC MOSFET module with series-parallel hybrid connection of 1200V/50A dies","authors":"Q. Xiao, Yang Yan, Xinke Wu, Na Ren, Kuang Sheng","doi":"10.1109/ISPSD.2015.7123461","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123461","url":null,"abstract":"In this paper, an innovative series-parallel hybrid circuit topology with silicon carbide MOSFETs is presented and analyzed. This topology consists of two uniform parts in parallel and each of the parts includes three sub-parts in series. The sub-part contains three primary parts connected in string where each of these primary parts has a parallel of two SiC MOSFETs. These 36 SiC devices are divided into six sub-parts, which are driven by a common driving signal. A 10kV/200A SiC MOSFETs module is fabricated based on this hybrid topology with thirty-six 1200V/50A SiC MOSFET dies. The dynamic switching behavior of the module is analyzed and double-pulse tests have been performed at 5400V/200A. The results show a good switching speed of 100ns in turn-on process and 200ns in turn-off process.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123988314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A breakthrough concept of HVICs for high negative surge immunity 高负浪涌免疫的hvic突破性概念
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123388
A. Jonishi, Masashi Akahane, M. Yamaji, H. Kanno, Takahide Tanaka, Noriyuki Tochinai, H. Sumida
{"title":"A breakthrough concept of HVICs for high negative surge immunity","authors":"A. Jonishi, Masashi Akahane, M. Yamaji, H. Kanno, Takahide Tanaka, Noriyuki Tochinai, H. Sumida","doi":"10.1109/ISPSD.2015.7123388","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123388","url":null,"abstract":"A new technology concept of HVICs which realizes high negative surge immunity has been proposed for junction-isolation (JI) or self-isolation (SI) processes. The basic concept is to isolate a substrate from the ground level to block the surge current. A new 1200V-class HVIC based on the new concept has been fabricated. The new HVIC has shown more than 10x higher negative surge immunity.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132215237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Static and dynamic performance characterization and comparison of 15 kV SiC MOSFET and 15 kV SiC n-IGBTs 15 kV SiC MOSFET和15 kV SiC n- igbt的静态和动态性能表征及比较
2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI: 10.1109/ISPSD.2015.7123431
Gangyao Wang, A. Huang, Fei Wang, Xiaoqing Song, Xijun Ni, S. Ryu, D. Grider, M. Schupbach, J. Palmour
{"title":"Static and dynamic performance characterization and comparison of 15 kV SiC MOSFET and 15 kV SiC n-IGBTs","authors":"Gangyao Wang, A. Huang, Fei Wang, Xiaoqing Song, Xijun Ni, S. Ryu, D. Grider, M. Schupbach, J. Palmour","doi":"10.1109/ISPSD.2015.7123431","DOIUrl":"https://doi.org/10.1109/ISPSD.2015.7123431","url":null,"abstract":"This paper presents the static and dynamic performance of 15 kV SiC IGBTs with 2 um and 5 um field-stop buffer layer thicknesses respectively and compares them with 15 kV SiC MOSFET in term of loss and switching capability. Their switching energy for different gate resistors and temperature have been reported and compared. A 5 kHz 10.5 kW 8 kV boost converter has been built and tested using these three devices respectively. The MOSFET based boost converter has the highest efficiency 99.39% which is the highest reported efficiency for a high voltage SiC device based converter. PLECS loss models can be developed for these devices based on the characterization data to simplify the simulation of a variety circuits or applications which potentially utilize these devices.","PeriodicalId":289196,"journal":{"name":"2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127495639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
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