下一代650V CSTBTTM采用先进的薄晶片技术制造，具有改进的SOA

2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD) Pub Date : 2015-05-10 DOI:10.1109/ISPSD.2015.7123381

R. Kamibaba, Kazuya Konishi, Y. Fukada, A. Narazaki, M. Tarutani

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引用次数: 20

摘要

采用先进的薄晶片技术，我们成功地制造了下一代650V级IGBT，具有改进的SOA，并保持了工业应用中电气特性的窄分布。应用的技术是更精细的晶体管电池，薄晶片工艺和优化的背面掺杂浓度分布。通过良好的背面晶圆工艺，在不牺牲生产良率的情况下实现了几乎大的芯片。结果表明，与传统的穿孔(PT)结构相比，VCEsat-Eoff权衡关系和有源面积短路能量(ESC/ a)得到了改善。

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Next generation 650V CSTBTTM with improved SOA fabricated by an advanced thin wafer technology

Using an advanced thin wafer technology, we have successfully fabricated the next generation 650V class IGBT with an improved SOA and maintaining the narrow distribution of the electrical characteristics for industrial applications. The applied techniques were the finer pattern transistor cell, the thin wafer process and the optimized back side doping concentration profiles. With the well organized back-side wafer process, the practically large chip has achieved without any sacrifice of the production yield. As a results, VCEsat-Eoff trade-off relationship and an Energy of Short Circuit by active Area (ESC/A) are improved in comparison with the conventional Punch Through (PT) structure.

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2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)

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