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[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers最新文献

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An improved objective function for mincut circuit partitioning 一种改进的最小切割电路划分目标函数
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122558
C. Sechen, Dahe Chen
{"title":"An improved objective function for mincut circuit partitioning","authors":"C. Sechen, Dahe Chen","doi":"10.1109/ICCAD.1988.122558","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122558","url":null,"abstract":"An improved objective function has been added to the Kernighan-Lin (1970), Fiduccia-Mattheyses (1982) (KLFM) partitioning algorithm. The time complexity of the enhanced KLFM algorithm remains linear in the number of pins, and there is essentially no change in the CPU time requirements. Based on circuit bipartitioning tests with ten industrial circuits, the number of nets cut was reduced by as much as 55% with the new objective function. The average reduction in nets cut was 38%.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"14 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134073172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
Built-in self-test for large embedded CMOS folded PLAs 内置自检大型嵌入式CMOS折叠pla
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122501
R. Dandapani, R. K. Gulati, D. K. Goel
{"title":"Built-in self-test for large embedded CMOS folded PLAs","authors":"R. Dandapani, R. K. Gulati, D. K. Goel","doi":"10.1109/ICCAD.1988.122501","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122501","url":null,"abstract":"A built-in self-test (BIST) design method for large embedded CMOS folded programmable logic arrays (PLAs) is presented that is based on a deterministic, function-independent structural method. It requires about half the testing time and comparable area overhead of deterministic BIST methods applied to corresponding nonfolded PLAs. Tests to detect stuck-at, bridging, cross-point and stuck-open faults are given.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132979150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Boolean decomposition in multi-level logic optimization 多层次逻辑优化中的布尔分解
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122513
S. Devadas, Albert R. Wang, A. Newton, A. Sangiovanni-Vincentelli
{"title":"Boolean decomposition in multi-level logic optimization","authors":"S. Devadas, Albert R. Wang, A. Newton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1988.122513","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122513","url":null,"abstract":"Multiple-valued Boolean minimization is proposed as a technique for identifying and extracting good Boolean factors which can be used as strong divisors to minimize the literal count and the area of a multilevel logic network. Given a two-level logic function, a subset of inputs to the function is selected such that the number of good Boolean factors contained in this subset of inputs is large. If the targeted implementation is a set of interconnected PLAs, the different cube combinations given by the subset of inputs are re-encoded to reduce the number of product terms in the logic function. A novel algorithm for the re-encoding is given that is based on the notion of partial satisfaction of constraints. Algorithms have been developed that identify a set of factors which maximally decrease the literal count of the logic network when they are used as strong divisors. Results obtained on several benchmark examples that illustrate the efficacy of the techniques are presented.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131005571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
iEDISON: an interactive statistical design tool for MOS VLSI circuits 用于MOS VLSI电路的交互式统计设计工具
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122454
T. Yu, S. Kang, I. Hajj, T. Trick
{"title":"iEDISON: an interactive statistical design tool for MOS VLSI circuits","authors":"T. Yu, S. Kang, I. Hajj, T. Trick","doi":"10.1109/ICCAD.1988.122454","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122454","url":null,"abstract":"iEDISON optimizes the transistor sizes of a circuit so that its performance is least sensitive to manufacturing process fluctuations. iEDISON considers three methods for design optimization, namely, the response surface method, the Taguchi method, and the nonnested experimental design method. These methods use experimental designs and regression models to explore the statistical performance variations. The efficiency of the system is demonstrated by an example on clock-skew minimization.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133686073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Automatic layout of custom analog cells in ANAGRAM 自动布局自定义模拟单元在ANAGRAM
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122567
D. J. Garrod, Rob A. Rutenbar, L. Carley
{"title":"Automatic layout of custom analog cells in ANAGRAM","authors":"D. J. Garrod, Rob A. Rutenbar, L. Carley","doi":"10.1109/ICCAD.1988.122567","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122567","url":null,"abstract":"ANAGRAM models cell layout in the style of a macrocell place-and-route problem. Individual cell primitives (transistor-level objects of widely varying sizes) are the macrocells. Module generation techniques are used to generate these internal primitives and to preserve critical matching and symmetries. An annealing-based placement algorithm then places these primitives. This is followed by a novel line-expansion signal router, which includes mechanisms to avoid noise coupling due to internodal capacitances between the signal wires and shared parasitic resistances in the DC supply wiring and operates in an iterative improvement fashion to eliminate such violations. Layouts for several custom CMOS cells have been successfully generated. Circuit-simulation results based on cell extractions demonstrate the effectiveness of the crosstalk-avoidance mechanisms.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132765757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 76
Combining event and data-flow graphs in behavioral synthesis 在行为合成中结合事件图和数据流图
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122462
G. Borriello
{"title":"Combining event and data-flow graphs in behavioral synthesis","authors":"G. Borriello","doi":"10.1109/ICCAD.1988.122462","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122462","url":null,"abstract":"Combining event and data-flow graphs into a single unified representation is addressed. A unified behavior graph is presented, and the algorithms required to support automatic synthesis are obtained. The new descriptive conventions are shown to be concise and to possess straightforward mappings to hardware. The algorithms are demonstrated to be of practical complexity (O(n/sup 2/), where N is the number of interface events). A practical example demonstrates how the representation is used, and synthesis results from five examples show that the synthesized circuitry is comparable to that achieved with other automatic methods or by experienced human designers.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134483956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Hierarchical placement for macrocells: a 'meet in the middle' approach 巨细胞的分层放置:一种“在中间相遇”的方法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122549
B. Eschermann, W. Dai, E. Kuh, M. Pedram
{"title":"Hierarchical placement for macrocells: a 'meet in the middle' approach","authors":"B. Eschermann, W. Dai, E. Kuh, M. Pedram","doi":"10.1109/ICCAD.1988.122549","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122549","url":null,"abstract":"Placement and related aspects of the BEAR macrocell layout system are described. A combination of top-down and bottom-up heuristics is used to make best use of a hierarchical description. The interdependency of placement and routing is considered explicitly. Experimental results show a considerable improvement over previous approaches.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131661678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
NCUBE: an automatic test generation program for iterative logic arrays NCUBE:迭代逻辑阵列自动测试生成程序
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122542
A. Chatterjee, J. Abraham
{"title":"NCUBE: an automatic test generation program for iterative logic arrays","authors":"A. Chatterjee, J. Abraham","doi":"10.1109/ICCAD.1988.122542","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122542","url":null,"abstract":"NCUBE applies all possible input patterns to each array cell while ensuring that the effects of incorrect transitions are observable at the array outputs. If the array is testable with a constant number of test vectors irrespective of its size (C-testable), then NCUBE generates the constant-size test set for the array. If the array cannot be tested with a constant number of test vectors, then the test size is proportional either to the number of rows or columns of the array or to the number of cells. In that case, NCUBE generates a minimal or near-minimal test set that depends on the size of the array.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115739188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
iPRIDE: a parallel integrated circuit simulator using direct method iPRIDE:使用直接方法的并行集成电路模拟器
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122516
Mi-Chang Chang, I. Hajj
{"title":"iPRIDE: a parallel integrated circuit simulator using direct method","authors":"Mi-Chang Chang, I. Hajj","doi":"10.1109/ICCAD.1988.122516","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122516","url":null,"abstract":"A parallel circuit simulator, iPRIDE, which uses a direct solution method and runs on a shared-memory multiprocessor is described. The simulator is based on a multilevel node tearing approach which produces a nested bordered-block-diagonal (BBD) form of the circuit equation matrix. The parallel solution of the nested BBD matrix is described. Its efficiency is shown to depend on how the circuit is partitioned as well as the sequence in which the concurrent tasks (scheduling) are solved. A partitioning heuristic is proposed, assuming that an arbitrary number of processors is available. Scheduling methods are studied when the number of processors is fixed. A method for determining the optimal level of partitioning, which depends on the number of processors as well as the scheduling methods, is described. The program is implemented on an ALLIANT FX/8 multiprocessor with shared memory. The performance of the program is reported.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124008605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
MulCh: a multi-layer channel router using one, two, and three layer partitions 护根:使用一层、两层和三层分区的多层通道路由器
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122469
R. I. Greenberg, A. Ishii, A. Sangiovanni-Vincentelli
{"title":"MulCh: a multi-layer channel router using one, two, and three layer partitions","authors":"R. I. Greenberg, A. Ishii, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1988.122469","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122469","url":null,"abstract":"Chameleon, a channel router for three layers of interconnect, has been implemented to accept specification of an arbitrary number of layers. Chameleon is based on a strategy of decomposing the multilayer problem into two- and three-layer problems in which one of the layers is reserved primarily for vertical wire runs and the other layer(s) for horizontal runs. In some situations, however, it is advantageous to consider also layers that allow the routing of entire nets, using both horizontal and vertical wires. MulCh is a multilayer channel router that extends the algorithms of Chameleon in this direction. MulCh can route channels with any number of layers and automatically chooses a good assignment of wiring strategies to the different layers. In test cases, MulCh shows significant improvement over Chameleon in terms of channel width, net length, and number of vias.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125067420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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