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[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers最新文献

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Built-in current testing-feasibility study 内置当前测试-可行性研究
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122524
W. Maly, P. Nigh
{"title":"Built-in current testing-feasibility study","authors":"W. Maly, P. Nigh","doi":"10.1109/ICCAD.1988.122524","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122524","url":null,"abstract":"A testing methodology which applies built-in current sensors to detect abnormal currents in the power buses of functional blocks of CMOS ICs is proposed, that significantly improves the quality of VLSI circuit testing. A summary of simulation results and design experiments is presented to demonstrate the feasibility and to illustrate the applicability of the approach. The results suggest that built-in current testing could be a very powerful tool for overcoming basic bottlenecks in VLSI testing, providing very inexpensive testing, high-quality built-in testing, or on-chip concurrent reliability testing for high-quality fault-tolerant systems.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133645615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 208
Temperature measurement of simulated annealing placements 模拟退火位置的温度测量
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122561
Jonathan Rose, W. Klebsch, Jürgen Wolf
{"title":"Temperature measurement of simulated annealing placements","authors":"Jonathan Rose, W. Klebsch, Jürgen Wolf","doi":"10.1109/ICCAD.1988.122561","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122561","url":null,"abstract":"One way to reduce the computational requirements of simulated annealing placement algorithms is to use a faster heuristic to replace the early phase of simulated annealing. Such systems need to know the starting temperature for the annealing phase that makes the best use of the existing structure, yet provides an appropriate amount of improvement. A method for determining the temperature of an existing placement from an analysis of the probability distribution of the change in cost function is presented. Using this view, a novel definition of equilibrium is given and the equilibrium temperature of a placement is defined. Temperatures of placements produced both by a simulated annealing and a min-cut placement algorithm are measured.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133452692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
PACE: a parallel VLSI extractor on the Intel hypercube multiprocessor PACE: Intel超立方体多处理器上的并行VLSI提取器
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122521
K. Belkhale, P. Banerjee
{"title":"PACE: a parallel VLSI extractor on the Intel hypercube multiprocessor","authors":"K. Belkhale, P. Banerjee","doi":"10.1109/ICCAD.1988.122521","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122521","url":null,"abstract":"Hypercube multiprocessors achieve a cost-effective and feasible approach to supercomputing by directly connecting a large number of low-cost processors with local memory, which cooperate on tasks by message-passing. An efficient parallel algorithm to speed up the VLSI circuit extraction task on a hypercube multiprocessor is proposed. The basic approach consists of partitioning of a circuit into smaller regions, assigning each region to a processor of the hypercube, and having the processors cooperate in performing the extraction procedures. The algorithm supports the use of different models for electrical parameter calculations of varying degrees of accuracy and computational complexity. The algorithm has been implemented in a program called PACE (parallel circuit extractor) on the Intel iPSC/D4-MX hypercube. Speedup results for the algorithm on many realistic VLSI circuits are presented.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127066848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Input assignment algorithm for decoded-PLAs with multi-input decoders 带多输入解码器的译码pla输入分配算法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122552
Kuang-Chien Chen, S. Muroga
{"title":"Input assignment algorithm for decoded-PLAs with multi-input decoders","authors":"Kuang-Chien Chen, S. Muroga","doi":"10.1109/ICCAD.1988.122552","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122552","url":null,"abstract":"A heuristic algorithm for assigning input variables to the decoders of a decoded-programmable logic array (PLA) is presented. In this algorithm, the number of inputs to each decoder is not restricted to two and the area overhead incurred by using multi-input decoders is considered in the cost function. Experimental results show that the areas of multi-input decoded-PLAs designed by this algorithm are smaller in many cases than those of decoded-PLAs with two-input decoders or standard PLAs.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130988674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A symbolic analysis tool for analog circuit design automation 模拟电路设计自动化的符号分析工具
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122555
S. Seda, M. Degrauwe, W. Fichtner
{"title":"A symbolic analysis tool for analog circuit design automation","authors":"S. Seda, M. Degrauwe, W. Fichtner","doi":"10.1109/ICCAD.1988.122555","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122555","url":null,"abstract":"An analysis tool has been developed to generate symbolic design equations for analog circuits. This tool (SYNAP) works in conjunction with a symbolic mathematics program (MACSYMA) to create both exact and simplified analytic expressions needed for circuit design and forms the cornerstone of a non-fixed-topology analog circuit design system. SYNAP performs DC, AC, noise, and offset analyses for time-invariant analog circuits with one stable operating point and generates code for the new design system.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134123091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 78
Automatic synthesis and technology mapping of combinational logic 组合逻辑的自动合成与技术映射
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122550
R. Bergamaschi
{"title":"Automatic synthesis and technology mapping of combinational logic","authors":"R. Bergamaschi","doi":"10.1109/ICCAD.1988.122550","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122550","url":null,"abstract":"SKOL, a system for the synthesis of combinational logic using a library of cells that emphasizes technology-mapping algorithms, is described. It combines current multilevel optimization techniques with a novel approach to technology mapping. Each factor (or the factorized Boolean equation) can be implemented by itself or collapsed into the higher level expression containing it, which is then implemented. An expression can be implemented in several ways, which differ in the degree of factorization. A number of selected implementations is evaluated and the one with minimal cost (area or delay) is chosen. The mapping algorithms are independent of the library of cells, which can be easily modified. Results from benchmark examples were better than or comparable to those for existing systems.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133545121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A grid generation system for process and device simulation 用于过程和设备仿真的网格生成系统
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122475
Akio Yajima, Hirofumi Jonishi, A. Maruyama
{"title":"A grid generation system for process and device simulation","authors":"Akio Yajima, Hirofumi Jonishi, A. Maruyama","doi":"10.1109/ICCAD.1988.122475","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122475","url":null,"abstract":"A method for numerically generating boundary-fitted coordinate systems for arbitrarily shaped three-dimensional regions such as LOCOS (local oxidation of silicon) isolation regions, trench cells, or stacked capacitor cells for next-generation DRAMs is presented. The three-dimensional region of interest is decomposed into curve-bounded surfaces which are free-form surfaces defined by spline curves. Grid points for the surfaces are generated by the boundary-fitted coordinate method, which improves convergence and accuracy. The usefulness of this system is illustrated through a series of examples and applications in semiconductor process and device simulation.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133036307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new global router for row-based layout 一个新的基于行布局的全局路由器
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122489
Kai-Win Lee, C. Sechen
{"title":"A new global router for row-based layout","authors":"Kai-Win Lee, C. Sechen","doi":"10.1109/ICCAD.1988.122489","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122489","url":null,"abstract":"A global router for row-based layout styles such as sea-of-gates, gate-array, and standard cell circuits is discussed. It is part of the latest version of TimberWolfSC, a placement and routing package for row-based layout. The algorithm outperformed the UTMC Highland system on two standard benchmark circuits. In tests on ten circuits, the global router produced track counts which were an average of 27% lower than those of the previous TimberWolfSC global router. The router is an average of 30 times faster than the previous algorithm. It has been generalized to handle macro blocks on the chip, equivalent sets of pins, single pins (those without an equivalent), and circuits having many or no built-into-the-cell feeds. Indiscriminate over-the-cell routing is also handled.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117137905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 89
Performance enhancements in BOLD using 'implications' 使用“隐含”增强BOLD的性能
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122470
G. Hachtel, R. Jacoby, P. Moceyunas, C. Morrison
{"title":"Performance enhancements in BOLD using 'implications'","authors":"G. Hachtel, R. Jacoby, P. Moceyunas, C. Morrison","doi":"10.1109/ICCAD.1988.122470","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122470","url":null,"abstract":"Uses of implied network values or conditions in the context of multilevel logic synthesis are presented. The use of these implications has resulted in performance-enhanced versions, ESPRESSOMLT2 and MLTAUT2, of the two cornerstone tools of the BOLD system, ESPRESSOMLT (multilevel logic minimizer based on tautology checking) and MLTAUT (multilevel logic verifier). The relationship between the implied values and the intermediate don't care set is presented. Then it is shown how this relationship can be exploited to reduce the number of tautology calls and the number of leaves in the binary recursion tree of tautology checking. A parallelized version MLTAUT2P, which runs on a Sun 3/75 LAN, is discussed. ESPRESSOMLT2, is expected to have speedups of up to a factor of 20 and the parallelized version a factor of over 100.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115793861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
CLAY: a malleable-cell multi-cell transistor matrix approach for CMOS LAYout synthesis CLAY:一种用于CMOS布局合成的可延展单元多单元晶体管矩阵方法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122481
P. Kollaritsch, S. Lusky, S. Prasad, Neil Potter
{"title":"CLAY: a malleable-cell multi-cell transistor matrix approach for CMOS LAYout synthesis","authors":"P. Kollaritsch, S. Lusky, S. Prasad, Neil Potter","doi":"10.1109/ICCAD.1988.122481","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122481","url":null,"abstract":"CLAY takes a netlist partitioned down to the transistor level, a technology file with an arbitrary number of metal layers, and constraints on aspect and I/O signal positions to produce mask geometries. CLAY attempts to capture, in software, layout knowledge at the transistor level (allowing variable-shaped cells including heights) and at the floorplan level for VLSI sized examples. CLAY compares well with standard cell and manual approaches.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"26 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120890269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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