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[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers最新文献

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CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits CHAMP:用于VLSI电路仿真的并发分层和多级程序
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122503
D. Saab, R. Mueller-Thuns, D. Blaauw, J. Abraham, J. T. Rahmeh
{"title":"CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits","authors":"D. Saab, R. Mueller-Thuns, D. Blaauw, J. Abraham, J. T. Rahmeh","doi":"10.1109/ICCAD.1988.122503","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122503","url":null,"abstract":"The design and implementation of a hierarchical switch-level simulator for complex digital circuits is discussed. The hierarchy is exploited to reduce the memory requirements of the simulation, thus allowing the simulation of circuits that are too large to simulate at the flat level. The algorithm used in the simulator operates directly on the hierarchical circuit description. Speedup is obtained through the use of high-level models. The simulator has been implemented on a SUN workstation and used to simulate a switch-level description of the Motorola 68000 microprocessor.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126791838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Vectorized fault simulation on the Cray X-MP supercomputer 克雷X-MP超级计算机上的矢量化故障模拟
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122493
F. Özgüner, R. Daoud
{"title":"Vectorized fault simulation on the Cray X-MP supercomputer","authors":"F. Özgüner, R. Daoud","doi":"10.1109/ICCAD.1988.122493","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122493","url":null,"abstract":"A highly vectorized parallel fault simulation (VPFS) algorithm developed to take advantage of the specific hardware architecture of the Cray X-MP is described. The data structure is optimized to suit the constraints imposed by the design of the main memory on the Cray supercomputer. The implementation of VPFS on a Cray X-MP/24 achieved a peak performance of about 2.5*10/sup 9/ gate evaluations per second on one processor, for a maximal speedup of approximately=30 over scalar processing.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126933731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Experiments in logic optimization 逻辑优化实验
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122512
M. Lightner, W. Wolf
{"title":"Experiments in logic optimization","authors":"M. Lightner, W. Wolf","doi":"10.1109/ICCAD.1988.122512","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122512","url":null,"abstract":"A number of experiments have been conducted to answer several important questions about logic optimization and its application to high-level synthesis. The experiments are summarised and show that: logic optimization is competitive with manual design; stronger optimization methods give somewhat better average results (10%-30%) at much greater computational cost (8* and more); fast logic optimization methods can be used to estimate the average results of the more powerful, costly methods; and literal count is a good estimator of area before routing for standard cell designs.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126025082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Net characterization based channel router: FT router 基于网络特性的通道路由器:FT路由器
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122468
H. Zhu, R. Fujii
{"title":"Net characterization based channel router: FT router","authors":"H. Zhu, R. Fujii","doi":"10.1109/ICCAD.1988.122468","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122468","url":null,"abstract":"General heuristic algorithms that have been developed for channel routing fail to fully characterize the 'landscape' of nets to be routed and thus may yield suboptimal solutions. The authors' track-assignment type routing algorithm makes use of an extensive set of net characteristics/relationships to perform a more sophisticated search for an optimal routing layout than the less other channel routers. When a routing problem is encountered, the algorithm resorts to subdoglegging, to a single-layer segment, or to local backtracking when a solution cannot be found. The algorithm can obtain optimal solutions for all the published channel routing examples. With some multiple-cycle examples, it performs better than the public-domain channel routers such as YACR2, Chameleon, or Mighty.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123914039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Simulating mixed analog-digital circuits on a digital simulator 在数字模拟器上模拟混合模数电路
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122505
D. Thelen, J. MacDonald
{"title":"Simulating mixed analog-digital circuits on a digital simulator","authors":"D. Thelen, J. MacDonald","doi":"10.1109/ICCAD.1988.122505","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122505","url":null,"abstract":"Time-domain simulation of circuits which contain analog functional blocks such as gain stages, filters and analog-digital conversion modules can be concurrently simulated with digital components on an event-driven digital simulator. A technique for modeling such analog circuits using digital behavior models has been developed. The simulation of mixed analog-digital circuits based on this methodology has been implemented on an accelerated digital simulator. An automated gain control circuit is presented as an example.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"41 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132537071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An efficient macromodeling approach for statistical IC process design 统计集成电路工艺设计中一种有效的宏观建模方法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122453
K. Low, S. W. Director
{"title":"An efficient macromodeling approach for statistical IC process design","authors":"K. Low, S. W. Director","doi":"10.1109/ICCAD.1988.122453","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122453","url":null,"abstract":"An efficient macromodeling approach for statistical IC process design based on experimental design and regression analysis is described. Automatic selection of the input variables is done as part of the model building procedure to reduce the problem dimension to a manageable size. The resulting macromodels are simple analytical expressions describing the device characteristics in terms of the fundamental process variables. The validity and efficiency of the macromodels obtained by the approach are illustrated through their use in an IC process device design centering example.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134510678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Bisim: a simulator for custom ECL circuits Bisim:定制ECL电路的模拟器
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122463
R. Kao, Bob Alverson, M. Horowitz, D. Stark
{"title":"Bisim: a simulator for custom ECL circuits","authors":"R. Kao, Bob Alverson, M. Horowitz, D. Stark","doi":"10.1109/ICCAD.1988.122463","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122463","url":null,"abstract":"Bisim is an event-driven, transistor-level, logic simulator that models both the logical and timing characteristics of custom emitter-coupled-logic/current-mode-logic circuits. Node voltages are represented by piecewise-linear waveforms, transistor currents are represented by piecewise-constant waveforms, and transistors are modeled as voltage-controlled current switches. Bisim's realistic circuit models enable it to simulate correctly a wide variety of circuit topologies while retaining much of the speed of higher level simulators.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124623913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A new algorithm for topological routing and via minimization 拓扑路由的一种新算法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122539
Xiong Xiao-ming
{"title":"A new algorithm for topological routing and via minimization","authors":"Xiong Xiao-ming","doi":"10.1109/ICCAD.1988.122539","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122539","url":null,"abstract":"A topological method for two-layer routing of printed circuit boards and VLSI chips is presented. The primary criterion is via minimization. Multiterminal nets and multiple wires are allowing to intersect at any via. After topological routing, the via minimization problem is then formulated as a (0, 1) linear programming problem and solved. The time and space complexities of the algorithm are O(n/sup 2/) and O(n+k), respectively, where n is the number of terminals in the routing region and k is the total number of cross points and via candidates.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124632263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
ECSTASY: a new environment for IC design optimization ECSTASY:集成电路设计优化的新环境
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122554
J. Shyu, A. Sangiovanni-Vincentelli
{"title":"ECSTASY: a new environment for IC design optimization","authors":"J. Shyu, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1988.122554","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122554","url":null,"abstract":"Interfacing to SPICE3 with sensitivity computation capability, ECSTASY features a forms-based, menu-driven user interface for problem formulation and user interaction, superlinearly convergent gradient-based algorithms, and a robust controlled random search procedure for circuit optimization. The optimization algorithms, problem formulation, and user interaction are discussed, and experimental results are given.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121978783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
Partitioning issues in circuit simulation on multiprocessors 多处理器电路仿真中的分区问题
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122515
David C. Yeh, V. Rao
{"title":"Partitioning issues in circuit simulation on multiprocessors","authors":"David C. Yeh, V. Rao","doi":"10.1109/ICCAD.1988.122515","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122515","url":null,"abstract":"A decomposition technique known as node tearing is used to perform circuit simulation on a multiprocessor. The effect of partitioning the circuit on the final speedup achieved is considered. Using a very simple model for the LU decomposition time of sparse matrices, a circuit-partitioning problem based on node tearing is formulated to maximize speedup on a multiprocessor. An abstract hypergraph partitioning problem is then posed along with an algorithm for its solution. The original circuit partitioning problem is then transformed into an equivalent hypergraph partitioning problem, thereby generating partitions for the circuit. The effect of the tradeoff of circuit-partitioning time versus the number of available processors on the speedup factor is also studied.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122326009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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