{"title":"拓扑路由的一种新算法","authors":"Xiong Xiao-ming","doi":"10.1109/ICCAD.1988.122539","DOIUrl":null,"url":null,"abstract":"A topological method for two-layer routing of printed circuit boards and VLSI chips is presented. The primary criterion is via minimization. Multiterminal nets and multiple wires are allowing to intersect at any via. After topological routing, the via minimization problem is then formulated as a (0, 1) linear programming problem and solved. The time and space complexities of the algorithm are O(n/sup 2/) and O(n+k), respectively, where n is the number of terminals in the routing region and k is the total number of cross points and via candidates.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"92 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A new algorithm for topological routing and via minimization\",\"authors\":\"Xiong Xiao-ming\",\"doi\":\"10.1109/ICCAD.1988.122539\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A topological method for two-layer routing of printed circuit boards and VLSI chips is presented. The primary criterion is via minimization. Multiterminal nets and multiple wires are allowing to intersect at any via. After topological routing, the via minimization problem is then formulated as a (0, 1) linear programming problem and solved. The time and space complexities of the algorithm are O(n/sup 2/) and O(n+k), respectively, where n is the number of terminals in the routing region and k is the total number of cross points and via candidates.<<ETX>>\",\"PeriodicalId\":285078,\"journal\":{\"name\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"volume\":\"92 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCAD.1988.122539\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.1988.122539","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new algorithm for topological routing and via minimization
A topological method for two-layer routing of printed circuit boards and VLSI chips is presented. The primary criterion is via minimization. Multiterminal nets and multiple wires are allowing to intersect at any via. After topological routing, the via minimization problem is then formulated as a (0, 1) linear programming problem and solved. The time and space complexities of the algorithm are O(n/sup 2/) and O(n+k), respectively, where n is the number of terminals in the routing region and k is the total number of cross points and via candidates.<>