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[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers最新文献

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Compaction of ATPG-generated test sequences for sequential circuits 序列电路中atpg生成的测试序列的压缩
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-12-01 DOI: 10.1109/ICCAD.1988.122533
R. Roy, T.M. Niermann, J. Patel, J. Abraham, R. Saleh
{"title":"Compaction of ATPG-generated test sequences for sequential circuits","authors":"R. Roy, T.M. Niermann, J. Patel, J. Abraham, R. Saleh","doi":"10.1109/ICCAD.1988.122533","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122533","url":null,"abstract":"Currently available automatic test pattern generators (ATPGs) generate test sets that are nonoptimal in length. The authors describe novel heuristic techniques to reduce the length of the test set for a sequential circuit by compaction of the automatically generated patterns. Based on these techniques, a program has been written in C that achieved a 56%-73% reduction in the test length of a highly sequential circuit obtained from industry.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131541986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
Analog circuit synthesis for performance in OASYS 模拟电路的合成性能在OASYS
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-12-01 DOI: 10.1109/ICCAD.1988.122556
R. Harjani, Rob A. Rutenbar, L. Carley
{"title":"Analog circuit synthesis for performance in OASYS","authors":"R. Harjani, Rob A. Rutenbar, L. Carley","doi":"10.1109/ICCAD.1988.122556","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122556","url":null,"abstract":"Mechanisms needed to meet stringent performance demands in a hierarchically structured analog circuit synthesis tool are described. Experiences with adding a high-speed comparator design style to the OASYS synthesis tool are discussed. It is argued that design iteration (the process of making a heuristic design choice, following it through to possible failure, then diagnosing the failure and modifying the overall plan of attack for the synthesis) is essential to meet such performance demands. Examples of high-speed comparators automatically synthesized by OASYS are presented. Designs competitive in quality with manual expert designs, e.g. with response time of 6 ns and input drive of 1 mV, can be synthesized in under 5 seconds on a workstation.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115547673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
The logic automation approach to accurate and efficient gate and functional level simulation 采用逻辑自动化方法实现准确高效的门级和功能级仿真
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122504
M. Heydemann, D. Dure
{"title":"The logic automation approach to accurate and efficient gate and functional level simulation","authors":"M. Heydemann, D. Dure","doi":"10.1109/ICCAD.1988.122504","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122504","url":null,"abstract":"Applying a mathematical formalism to event-driven simulation has led to model correctness and highly efficient implementation. MSI functional models with accurate delays are compiled into transition tables for elementary state machines that are interconnected to model networks. Simulation consists of computing the state trajectories of these machines using the generated state transition tables. A simulation speed of 50000 event/seconds per MIPS has been obtained during runtime experiments on a simulation system based on these techniques. This order-of-magnitude speedup is due in part to the use of a novel delay model that improves on the usual inertial rise/fall model.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115448610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A fast algorithm for the optimal state assignment of large finite state machines 大型有限状态机最优状态分配的快速算法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122483
D. Varma, E. Trachtenberg
{"title":"A fast algorithm for the optimal state assignment of large finite state machines","authors":"D. Varma, E. Trachtenberg","doi":"10.1109/ICCAD.1988.122483","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122483","url":null,"abstract":"A state-assignment procedure is presented that uses only abstract complexity criteria and produces assignments that are not targeted toward particular implementations. It produces networks similar in complexity to those obtained by contemporary methods but is an order of magnitude faster, because it does not use computationally expensive logic synthesis algorithms to predict the effect of assignment on synthesis. Assignments for finite-state machines typically took about 10 minutes on a VAX 11/780.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125134150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Current estimation in MOS IC logic circuits MOS IC逻辑电路中的电流估计
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122496
S. Chowdhury, J. Barkatullah
{"title":"Current estimation in MOS IC logic circuits","authors":"S. Chowdhury, J. Barkatullah","doi":"10.1109/ICCAD.1988.122496","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122496","url":null,"abstract":"Estimation of currents in NMOS/CMOS IC logic circuits at the gate and macro levels is considered. The estimates are to be used for reliable design of power and ground buses. An accurate and efficient model of a gate is used to develop algorithms to estimate the maximum currents. The algorithms provide a tradeoff between run time and the quality of solution. Experimental results are included.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126157268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A dormant subcircuit model for maximizing iteration latency 最大化迭代延迟的休眠子电路模型
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122544
P. Cox, R. Burch, Ping Yang
{"title":"A dormant subcircuit model for maximizing iteration latency","authors":"P. Cox, R. Burch, Ping Yang","doi":"10.1109/ICCAD.1988.122544","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122544","url":null,"abstract":"An approach for modeling dormant subcircuits is presented that utilizes iteration latency to provide speed improvements that are comparable to the potential speed improvements of an independent time step approach. This scheme minimizes the work required on the first iteration at a time point, which is the normal limiting factor in iteration latency schemes. However, since simulations are performed for each subcircuit at each time point, the penalty for backing up when truncation error is unacceptable is minimized.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130405057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Automatic synthesis of a multi-bus architecture for DSP DSP多总线结构的自动合成
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122459
B. Haroun, M. Elmasry
{"title":"Automatic synthesis of a multi-bus architecture for DSP","authors":"B. Haroun, M. Elmasry","doi":"10.1109/ICCAD.1988.122459","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122459","url":null,"abstract":"An architectural synthesis methodology for a multibus multifunctional unit processor is presented. It is implemented as part of a design aid tool called SPAID. The input to SPAID is a DSP flow graph algorithm description with the required throughput and latency. The synthesized processor is a self-timed element externally, while it is internally synchronous and suitable for a systolic multiprocessor implementation for large DSP applications. For a benchmark elliptic filter algorithm SPAID synthesizes architectures with a linear topology that use fewer interconnects and multiplexers than other systems synthesizing random-topology architectures for the same throughput.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"3 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127013841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
PYRAMID-a hierarchical waveform relaxation-based circuit simulation program 基于分层波形松弛的电路仿真程序
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122545
P. Saviz, O. Wing
{"title":"PYRAMID-a hierarchical waveform relaxation-based circuit simulation program","authors":"P. Saviz, O. Wing","doi":"10.1109/ICCAD.1988.122545","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122545","url":null,"abstract":"A hierarchical waveform-relaxation-based method for analysis of bipolar, MOS, and GaAs FET circuits is presented. By analyzing the circuit in a hierarchical manner, a faster solution has been obtained for circuits exhibiting strong bidirectionality and feedback than has previously been possible. The technique has been applied to a wide variety of digital and mixed analog/digital circuits, and circuits containing over 18000 transistors have been analyzed. Results obtained for a variety of circuits show up to two orders of magnitude improvement in computation time compared to conventional circuit simulation techniques and up to one order of magnitude improvement compared to the standard waveform-relaxation technique.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125682683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Automatically extracting structure from a logical design 自动从逻辑设计中提取结构
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122548
Mark Hirsch, D. Siewiorek
{"title":"Automatically extracting structure from a logical design","authors":"Mark Hirsch, D. Siewiorek","doi":"10.1109/ICCAD.1988.122548","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122548","url":null,"abstract":"An algorithm for extracting structure from a logical design is presented. It uses a data structure which explicitly represents not only connectivity, but also a variety of information that is generated during logical design. The algorithm is applied to a small design and used to determine the layout. Work is in progress to increase the number of functional cluster types that can be extracted and to develop additional heuristics for automatically mapping the structure onto the chip.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132506383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Technology mapping for standard-cell generators 标准单元生成器的技术映射
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122551
Michel Berkelaar, J. Jess
{"title":"Technology mapping for standard-cell generators","authors":"Michel Berkelaar, J. Jess","doi":"10.1109/ICCAD.1988.122551","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122551","url":null,"abstract":"A novel approach to technology mapping that produces a standard-cell IC implementation from a previously optimized and decomposed set of Boolean functions is presented. Instead of trying to solve the problem for random libraries of standard cells, which proved to be very difficult, it has been solved for cell generators, which are only limited by technology constraints. The completeness of the sets of cells that can be generated by a cell generator, given a certain technology, makes it possible to use an elegant mapping algorithm. The algorithm was coded in CommonLISP, and used to map a large number of benchmark examples. The results compare favorably with published results.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130259952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
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