Automatic synthesis of a multi-bus architecture for DSP

Abstract

An architectural synthesis methodology for a multibus multifunctional unit processor is presented. It is implemented as part of a design aid tool called SPAID. The input to SPAID is a DSP flow graph algorithm description with the required throughput and latency. The synthesized processor is a self-timed element externally, while it is internally synchronous and suitable for a systolic multiprocessor implementation for large DSP applications. For a benchmark elliptic filter algorithm SPAID synthesizes architectures with a linear topology that use fewer interconnects and multiplexers than other systems synthesizing random-topology architectures for the same throughput.<>