R. Roy, T.M. Niermann, J. Patel, J. Abraham, R. Saleh
{"title":"序列电路中atpg生成的测试序列的压缩","authors":"R. Roy, T.M. Niermann, J. Patel, J. Abraham, R. Saleh","doi":"10.1109/ICCAD.1988.122533","DOIUrl":null,"url":null,"abstract":"Currently available automatic test pattern generators (ATPGs) generate test sets that are nonoptimal in length. The authors describe novel heuristic techniques to reduce the length of the test set for a sequential circuit by compaction of the automatically generated patterns. Based on these techniques, a program has been written in C that achieved a 56%-73% reduction in the test length of a highly sequential circuit obtained from industry.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"48","resultStr":"{\"title\":\"Compaction of ATPG-generated test sequences for sequential circuits\",\"authors\":\"R. Roy, T.M. Niermann, J. Patel, J. Abraham, R. Saleh\",\"doi\":\"10.1109/ICCAD.1988.122533\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Currently available automatic test pattern generators (ATPGs) generate test sets that are nonoptimal in length. The authors describe novel heuristic techniques to reduce the length of the test set for a sequential circuit by compaction of the automatically generated patterns. Based on these techniques, a program has been written in C that achieved a 56%-73% reduction in the test length of a highly sequential circuit obtained from industry.<<ETX>>\",\"PeriodicalId\":285078,\"journal\":{\"name\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"volume\":\"59 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"48\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCAD.1988.122533\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.1988.122533","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Compaction of ATPG-generated test sequences for sequential circuits
Currently available automatic test pattern generators (ATPGs) generate test sets that are nonoptimal in length. The authors describe novel heuristic techniques to reduce the length of the test set for a sequential circuit by compaction of the automatically generated patterns. Based on these techniques, a program has been written in C that achieved a 56%-73% reduction in the test length of a highly sequential circuit obtained from industry.<>