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[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers最新文献

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An efficient method for circuit sensitivity calculation using piecewise linear waveform models 一种利用分段线性波形模型计算电路灵敏度的有效方法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122455
S. Kang, Y. Leblebici
{"title":"An efficient method for circuit sensitivity calculation using piecewise linear waveform models","authors":"S. Kang, Y. Leblebici","doi":"10.1109/ICCAD.1988.122455","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122455","url":null,"abstract":"An efficient method for calculating the transient sensitivities in MOS circuits with respect to a large number of parameters is discussed. The approach uses simple circuit models built by piecewise-linearization of time-domain circuit responses. Closed-form expressions are derived for the calculation of transient sensitivities of the corresponding linear circuits. The transient sensitivity of the nonlinear circuit is then approximated as a simple function of individual linear circuit sensitivities. It is shown that the efficiency of this approach increases with the circuit size as well as with the number of sensitivity parameters considered.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116536533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new formulation of yield enhancement problems for reconfigurable chips 可重构芯片良率提高问题的新表述
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122562
N. Hasan, J. Cong, C. Liu
{"title":"A new formulation of yield enhancement problems for reconfigurable chips","authors":"N. Hasan, J. Cong, C. Liu","doi":"10.1109/ICCAD.1988.122562","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122562","url":null,"abstract":"The covering problem assigns redundant elements to replace defective elements so that the chip will function properly. A general model that can be used to represent the relationship between redundant elements and defective elements in a uniform way is presented. This model subsumes many of the models discussed in previous approaches. A complete characterization of the complexity of the covering problems in all the subcases of the model, most of which have not been studied before, is given. It is hoped that the formulation will also lead to new ways of designing reconfigurable chips.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"10 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123279804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
CMOS inverter delay and other formulas using alpha -power law MOS model CMOS逆变器延时等公式采用alpha -幂律MOS模型
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122466
T. Sakurai
{"title":"CMOS inverter delay and other formulas using alpha -power law MOS model","authors":"T. Sakurai","doi":"10.1109/ICCAD.1988.122466","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122466","url":null,"abstract":"A simple yet realistic MOS model called the alpha -power-law CMOS model which includes the carrier velocity saturation effect important in short-channel MOSFETs, is introduced. The model is an extension of Shockley's square law-MOS model in the saturation region. Using the model, closed-form expressions are derived for the delay, short-circuit power, and transition voltage of CMOS inverters. The resultant delay expression includes input waveform slope effects and parasitic drain/source resistance effects and can be used in simulation and/or optimization CAD tools. It is shown that the CMOS inverter delay becomes less sensitive to the input waveform slope and the short-circuit dissipation increases as MOSFETs become small.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123327566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Stick diagram extraction program SKELETON 框图提取程序SKELETON
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122519
Masayuki Sato, N. Ohba, Hiromi Watanabe, Shozo Saito
{"title":"Stick diagram extraction program SKELETON","authors":"Masayuki Sato, N. Ohba, Hiromi Watanabe, Shozo Saito","doi":"10.1109/ICCAD.1988.122519","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122519","url":null,"abstract":"A stick diagram extraction program SKELETON has been developed to make use of an existing handcrafted layout in a symbolic circuit layout system. It transforms a physical layout into an equivalent stick diagram. The concepts of centralized terminals and dispersed terminals are used for technology change and scaling. A heuristic procedure is presented to reduce jogs.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128856262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On the design of robust multiple fault testable CMOS combinational logic circuits 鲁棒多故障可测试CMOS组合逻辑电路的设计
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122502
S. Kundu, S. Reddy, N. Jha
{"title":"On the design of robust multiple fault testable CMOS combinational logic circuits","authors":"S. Kundu, S. Reddy, N. Jha","doi":"10.1109/ICCAD.1988.122502","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122502","url":null,"abstract":"Tests that detect modeled faults independent of the delays in the circuit under test are called robust tests. An integrated approach to the design of combinational logic circuits in which all single stuck-open faults and path delay faults are detectable by robust tests was presented by the authors earlier. It is shown that the earlier design actually results in circuits in which all multiple stuck-at and stuck-open and multipath delay faults are robustly testable. The tests to detect such faults are presented.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127596231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
Taking advantage of optimal on-chip parallelism for parallel discrete-event simulation 利用片上最优并行性进行并行离散事件仿真
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122518
J. V. Briner, J. L. Ellis, G. Kedem
{"title":"Taking advantage of optimal on-chip parallelism for parallel discrete-event simulation","authors":"J. V. Briner, J. L. Ellis, G. Kedem","doi":"10.1109/ICCAD.1988.122518","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122518","url":null,"abstract":"The optimal level of performance from parallel discrete-event simulation depends on the circuit being simulated, the vectors being simulated, and the machine on which the simulation is being performed. Empirical studies based on very simple models suggest that the amount of parallelism available in typical circuits is very small. A model of optimal performance for a machine with an infinite number of processors having uniform memory accesses is presented. It demonstrates that some circuits have significantly more parallelism than previously believed. The model is refined to define the optimal load partitioning for a machine with a finite number of processors with uniform access and extended to define the optimal static data partitioning. A metric is obtained which can be used to benchmark different models of parallel simulation. The effectiveness of these models in detecting performance problems of the version of RSIM running on the BBN Butterfly is shown.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114845098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Expanded rectangles: a new VLSI data structure 扩展矩形:一种新的VLSI数据结构
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122566
M. Quayle, Jon A. Solworth
{"title":"Expanded rectangles: a new VLSI data structure","authors":"M. Quayle, Jon A. Solworth","doi":"10.1109/ICCAD.1988.122566","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122566","url":null,"abstract":"A data structure derived from corner stitching which allows efficient representation of VLSI layouts is presented. While each entry in the expanded rectangle database is larger than the corresponding corner-stitched entry, generally fewer entries are required to represent the same VLSI layout. The data structure has two important features: first, the VLSI design is represented as a slicing structure in which each slice contains a portion of the solid material; and second, corner stitches are used to provide two-dimensional nearness information. Initial measurements indicate that expanded rectangles is a viable data structure for use in a complete VLSI layout system.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128868218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
First order nonlinear device bypass in circuit simulation 电路仿真中一阶非线性器件旁路
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122543
Bill Nye
{"title":"First order nonlinear device bypass in circuit simulation","authors":"Bill Nye","doi":"10.1109/ICCAD.1988.122543","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122543","url":null,"abstract":"The current bypass scheme used in SPICE produces inconsistent approximations to the function and derivative values needed by Newton iteration. A consistent first-order bypass approach based on the first-degree Taylor polynomial at the previous evaluation point is introduced. Test results show moderate reductions in the number of time points and Newton iterations during transient analyses, an increase in the percentage of devices that bypass, and a significant decrease in the average relative error of output waveforms. This last result suggests that comparable accuracy can be achieved with a considerably larger setting of the user-settable accuracy parameter, leading to a significant decrease in CPU time.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"316 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133636309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A fast fault simulation algorithm for combinational circuits 一种快速组合电路故障仿真算法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122486
W. Ke, S. Seth, B. Bhattacharya
{"title":"A fast fault simulation algorithm for combinational circuits","authors":"W. Ke, S. Seth, B. Bhattacharya","doi":"10.1109/ICCAD.1988.122486","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122486","url":null,"abstract":"The performance of a fast fault simulation algorithm for combinational circuits, such as the critical-path-tracing method, is determined primarily by the efficiency with which it can deduce the detectability of stem faults (stem analysis). A graph-based approach to perform stem analysis is proposed. A dynamic data structure, called the criticality constraint graph, is used during the backward pass to carry information related to self-masking and multiple-path sensitization of stem faults. The structure is updated in such a way that when stems are reached, their criticality can be found by looking at the criticality constraints on their fanout branches. Compared to the critical-path-tracing method, the algorithm is exact and does not require forward propagation of individual stem faults. Several examples which illustrate the power of the algorithm are given. Preliminary data on an implementation are also provided.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129841589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Cbase 1.0: a CAD database for VLSI circuits using object oriented technology 采用面向对象技术的VLSI电路CAD数据库
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122535
M. Breuer, W. H. Cheng, Rajiv Gupta, I. Hardonag, E. Horowitz, S. Y. Lin
{"title":"Cbase 1.0: a CAD database for VLSI circuits using object oriented technology","authors":"M. Breuer, W. H. Cheng, Rajiv Gupta, I. Hardonag, E. Horowitz, S. Y. Lin","doi":"10.1109/ICCAD.1988.122535","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122535","url":null,"abstract":"Cbase 1.0 is a multilayered system which provides a common repository of both VLSI objects and their associated operations, a tool interface for writing new applications, and a user interface for invoking applications or viewing objects in the database. Preliminary experience indicates that using an object-oriented database provides features such as specialization/generalization, property and operation inheritance, and polymorphism among object types which are useful for modeling the hierarchical nature and multiple views of a circuit.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123466644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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