Taking advantage of optimal on-chip parallelism for parallel discrete-event simulation

Abstract

The optimal level of performance from parallel discrete-event simulation depends on the circuit being simulated, the vectors being simulated, and the machine on which the simulation is being performed. Empirical studies based on very simple models suggest that the amount of parallelism available in typical circuits is very small. A model of optimal performance for a machine with an infinite number of processors having uniform memory accesses is presented. It demonstrates that some circuits have significantly more parallelism than previously believed. The model is refined to define the optimal load partitioning for a machine with a finite number of processors with uniform access and extended to define the optimal static data partitioning. A metric is obtained which can be used to benchmark different models of parallel simulation. The effectiveness of these models in detecting performance problems of the version of RSIM running on the BBN Butterfly is shown.<>