CMOS inverter delay and other formulas using alpha -power law MOS model

Abstract

A simple yet realistic MOS model called the alpha -power-law CMOS model which includes the carrier velocity saturation effect important in short-channel MOSFETs, is introduced. The model is an extension of Shockley's square law-MOS model in the saturation region. Using the model, closed-form expressions are derived for the delay, short-circuit power, and transition voltage of CMOS inverters. The resultant delay expression includes input waveform slope effects and parasitic drain/source resistance effects and can be used in simulation and/or optimization CAD tools. It is shown that the CMOS inverter delay becomes less sensitive to the input waveform slope and the short-circuit dissipation increases as MOSFETs become small.<>