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[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers最新文献

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Don't cares and global flow analysis of Boolean networks 不要在意布尔网络的全局流分析
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122471
R. Brayton, E. Sentovich, F. Somenzi
{"title":"Don't cares and global flow analysis of Boolean networks","authors":"R. Brayton, E. Sentovich, F. Somenzi","doi":"10.1109/ICCAD.1988.122471","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122471","url":null,"abstract":"External, intermediate, and fan-out don't care sets have been used to describe information about network structure required to optimize a node of a Boolean network locally. Another method to optimize a network has been called global flow analysis. The authors relate these approaches, generalize global flow to arbitrary Boolean networks, and suggest new algorithms for these problems.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130264663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
The use of inverse layout trees for hierarchical design verification 利用逆布局树进行分层设计验证
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122565
N. Hedenstierna, K. Jeppson
{"title":"The use of inverse layout trees for hierarchical design verification","authors":"N. Hedenstierna, K. Jeppson","doi":"10.1109/ICCAD.1988.122565","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122565","url":null,"abstract":"The authors present the inverse layout tree as a means of performing fully hierarchical design verification without any restrictions on subcell overlaps. This provides a fast and general method of marking design rule errors or extracted devices at the correct hierarchical level. The inverse layout tree for each element is built up as layout data is processed from the bottom up. When layout processing is completed one can go through the layout again and use the inverse layout trees to determine the most appropriate cell for each element. New elements formed as layout from different cells overlap can now be placed at the lowest level of hierarchy where they always appear instead of being indiscriminately incorporated in the parent cell. The method preserves the original hierarchy to the greatest possible extent. The method has been implemented in the corner-based design-rule checker and circuit extractor, Corny. As an important example it is shown that logical DIFF (ANDNOT) operations between layers can be performed fully hierarchically.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127946631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Efficient handling of large wiring data in TANGATE 有效地处理TANGATE中的大型布线数据
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122534
Tom Kronmiller
{"title":"Efficient handling of large wiring data in TANGATE","authors":"Tom Kronmiller","doi":"10.1109/ICCAD.1988.122534","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122534","url":null,"abstract":"Advances in VLSI have made possible gate-array designs containing over 100 K gates and as many as 50 K objects and 50 K nets. These large designs require the CAD database designer to support fast access to all information necessary for the physical layout of the chip while staying within restricted memory and disk space. The TANGATE database was specifically designed to meet these needs. A novel hierarchical wiring structure has resulted in an extremely compact representation for detailed routing information. Interfaces to support geometric searching have resulted in good performance, despite the overhead of unpacking the wiring data, and form the basis for many TANGATE algorithms.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124478884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new layout optimization methodology for CMOS complex gates 一种新的CMOS复杂栅极布局优化方法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122530
C. Y. Chen, C. Y. Hou
{"title":"A new layout optimization methodology for CMOS complex gates","authors":"C. Y. Chen, C. Y. Hou","doi":"10.1109/ICCAD.1988.122530","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122530","url":null,"abstract":"Efficient algorithms for the layout generation of CMOS complex gates are presented. Heuristics which use the concept of delayed binding are introduced. An optimized net list is decided during the layout generation phase, rather than before. Examples are given showing that this approach can achieve a considerable improvement over previous ones.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124705706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Carioca-A 'smart' and flexible switch-box router carioca“智能”和灵活的开关箱路由器
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122457
P. Dubois, A. Puissochet, Anne-Marie Tagant
{"title":"Carioca-A 'smart' and flexible switch-box router","authors":"P. Dubois, A. Puissochet, Anne-Marie Tagant","doi":"10.1109/ICCAD.1988.122457","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122457","url":null,"abstract":"A two-dimensional router utilizing two layers is presented. The routing technique can be described as follows: After partitioning of the nets into a set of subnets, the construction is carried out on a step-by-step basis, which allows the system to dynamically take into account new information. This part has been implemented with a blackboard architecture. The router can handle pins that are not on a grid on one set of parallel edges. To provide a solution to a given problem, the router expands the switch-box by adding rows dynamically where they are needed. Many test cases have been run successfully, and some results, including Burstein's difficult switch-box, are presented.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126123777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Parallel PLA fault simulation based on Boolean vector operations 基于布尔向量运算的并行PLA故障仿真
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122492
E. Chiprout, J. Rajski, M. Robinson
{"title":"Parallel PLA fault simulation based on Boolean vector operations","authors":"E. Chiprout, J. Rajski, M. Robinson","doi":"10.1109/ICCAD.1988.122492","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122492","url":null,"abstract":"An efficient PLA crosspoint fault simulation algorithm is presented. Parallel Boolean vector operations on a bitwise representation of PLA faults replace set operations, leading to increasing efficiency as the PLA size grows. Experimental results demonstrate execution times averaging over 100% faster than PLATYPUS and almost two and a half orders of magnitude faster than the CHIEFS fault simulator.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127464882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Doubly folded transistor matrix layout 双折叠晶体管矩阵布局
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122479
Lukas P. P. P. van Genneken, J. V. Eijndhoven, J. Brouwers
{"title":"Doubly folded transistor matrix layout","authors":"Lukas P. P. P. van Genneken, J. V. Eijndhoven, J. Brouwers","doi":"10.1109/ICCAD.1988.122479","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122479","url":null,"abstract":"A flexible module generator that lays out transistor net lists is presented. The formulation of this layout problem as a two-dimensional folding problem is novel. The folding algorithm uses an elegant hierarchical divide-and-conquer technique. The aspect ratio and pin positions can be controlled within a wide range, while the area remains approximately constant. Accurate control of the aspect ratio and pin positions is important in combination with top-down floorplanning. The mask generator uses a small library of adaptable transistors with parameters like length, width, positions of the terminals, and an optional diffusion implant. Compared to other automated layout approaches, the module generator makes smaller and more flexible layouts. The layout of the modules can be customized with respect to all major design parameters.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133749415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Floorplan design using distributed genetic algorithms 平面图设计采用分布式遗传算法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122547
J. Cohoon, Shailesh U. Hegde, W. Martin, D. Richards
{"title":"Floorplan design using distributed genetic algorithms","authors":"J. Cohoon, Shailesh U. Hegde, W. Martin, D. Richards","doi":"10.1109/ICCAD.1988.122547","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122547","url":null,"abstract":"A distributed algorithm for solving the floorplan design problem, called a genetic algorithm with punctuated equilibria (GAPE), is presented. Implementation details and the results of empirical studies are presented. The experiments have demonstrated that GAPE performs consistently better than a recently published simulated annealing approach, with respect to both the average cost of the solutions found and the best solution found.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131945002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
A new algorithm for CMOS gate matrix layout 一种新的CMOS栅极矩阵布局算法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122480
C. Y. Chen, C. Y. Hou
{"title":"A new algorithm for CMOS gate matrix layout","authors":"C. Y. Chen, C. Y. Hou","doi":"10.1109/ICCAD.1988.122480","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122480","url":null,"abstract":"Efficient algorithms for CMOS gate matrix layouts which have fully utilized the duality between NMOS and PMOS are presented. Improper assumptions made by previous authors are pointed out. Problems which have prevented previous algorithms from reaching a real optimal result are discussed and solved. Significant improvements are achieved over previous algorithms.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"5 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133076438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Codar: a congestion-directed general area router Codar:拥塞导向的通用区域路由器
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122456
Ping-San Tzeng, C. Séquin
{"title":"Codar: a congestion-directed general area router","authors":"Ping-San Tzeng, C. Séquin","doi":"10.1109/ICCAD.1988.122456","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122456","url":null,"abstract":"A general area router that integrates the phases of global routing and detailed routing has been developed. The global phase coarsely places the nets based on the congestion of the routing region, and the detailed phase modifies the course wiring to find legal positions for all wire segments. Both phases use the same grid space of routing tracks with two or more levels of interconnect. With this integrated data structure, the router can alternate between global and detailed routing operations, both of which use rip-up and reroute techniques. This integration has resulted in a router that can solve difficult problems not solvable by other programs while exhibiting runtimes that grow only moderately with the size of the routing problem.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116006462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
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