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[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers最新文献

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Automatic layout generation for CMOS operational amplifiers CMOS运算放大器的自动布局生成
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122568
Han Young Koh, C. Séquin, P. Gray
{"title":"Automatic layout generation for CMOS operational amplifiers","authors":"Han Young Koh, C. Séquin, P. Gray","doi":"10.1109/ICCAD.1988.122568","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122568","url":null,"abstract":"An analog silicon compiler for CMOS op amps (OPASYN) has been developed. The synthesis system takes as inputs system-level specifications, fabrication-dependent technology parameters, and geometric layout rules. Based on the general domain of the specifications, the program first selects an appropriate circuit topology from a database and determines optimal values for the set of design parameters so as to meet the design objectives. Subsequently, a mask-level layout for the given circuit with its optimized device sizes is constructed using an approach based on a few leaf-cell generators and on circuit-dependent slicing trees that guarantee sound arrangements of the individual components. The synthesis process is fast enough for the program to be used interactively at the system-design level by system engineers who are inexperienced in op amp design.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124206359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A new method for the efficient state-assignment of PLA-based sequential machines 基于pla的顺序机的高效状态分配新方法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122484
J. Huertas, J. Quintana
{"title":"A new method for the efficient state-assignment of PLA-based sequential machines","authors":"J. Huertas, J. Quintana","doi":"10.1109/ICCAD.1988.122484","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122484","url":null,"abstract":"A method for the state assignment of finite sequential machines is proposed. The algorithm gives solutions with a minimum number of state variables instead of with minimal-cardinality next-state functions. Comparisons between the results given by the proposed method and others previously reported have shown a clear superiority of the present algorithm in terms of silicon area, especially for big machines.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129456203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Critical path tracing in sequential circuits 顺序电路中的关键路径跟踪
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122485
P. R. Menon, Y. Levendel, M. Abramovici
{"title":"Critical path tracing in sequential circuits","authors":"P. R. Menon, Y. Levendel, M. Abramovici","doi":"10.1109/ICCAD.1988.122485","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122485","url":null,"abstract":"Critical path tracing has been shown to be faster than traditional fault simulation methods, but it produces pessimistic results in some cases involving reconvergent fanout. It is shown that the pessimistic nature of critical path tracing in combinational circuits can lead to incorrect results that are not necessarily pessimistic in sequential circuits. A modification of the method for removing the approximation is proposed, and a critical path tracing algorithm for synchronous sequential circuits is presented.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121426612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Modeling and enhancing virtual memory performance in logic simulation 逻辑仿真中虚拟内存性能的建模与增强
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122507
S. P. Smith, J. Kuban
{"title":"Modeling and enhancing virtual memory performance in logic simulation","authors":"S. P. Smith, J. Kuban","doi":"10.1109/ICCAD.1988.122507","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122507","url":null,"abstract":"To achieve acceptable performance, virtual memory systems generally rely on the presence of a high degree of spatial and temporal reference locality during code execution. The enormous quantity of intricately related data typically found in logic simulation makes this a dubious assumption. There simply is no way to statically organize circuit representation data to ensure locality. This phenomenon is explored through the analysis of address reference data obtained from a logic tester monitoring simulation execution on a general-purpose virtual memory workstation. Data from code compilation runs are included to illustrate the differences in reference behavior found between logic simulation and more conventional applications. An improved virtual memory management scheme based on speculative references and tuned to logic simulation is presented.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121360934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CLANS: a high-level synthesis tool for high resolution data converters CLANS:用于高分辨率数据转换器的高级综合工具
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122557
J. Kenney, L. Carley
{"title":"CLANS: a high-level synthesis tool for high resolution data converters","authors":"J. Kenney, L. Carley","doi":"10.1109/ICCAD.1988.122557","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122557","url":null,"abstract":"A high-level synthesis tool, CLANS, that accepts data converter performance specifications and selects optimal block-level component specifications for noise-shaping coders is presented. CLANS both predicts the performance of multibit noise-shaping coders (both A/D and D/A converters) and determines optimal loop-filter transfer functions. The performance of CLANS' designs has been verified using both block-level simulation and experimental measurements on a CMOS prototype D/A converter.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122972387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
BEATNP: a tool for partitioning Boolean networks 用于划分布尔网络的工具
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122452
Hyunwoo Cho, G. Hachtel, M. Nash, L. Setiono
{"title":"BEATNP: a tool for partitioning Boolean networks","authors":"Hyunwoo Cho, G. Hachtel, M. Nash, L. Setiono","doi":"10.1109/ICCAD.1988.122452","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122452","url":null,"abstract":"BEATNP (BoolEAn Tools Network Partitioner) was designed to extend the application size capability of the BOLD (Boulder Optimal Logic Design) system. BEATNP partitions a Boolean network into subnetworks which satisfy user specified size constraints. Most of the tools in the BOLD tools suite solve problems which are in NP or Co-NP, so they can be assumed to have exponential complexity. Because the BEATNP algorithms have log-linear worst-case complexity, the CPU time requirements of optimization tools can be reduced greatly in difficult cases. When used with the BOLD minimizer on a set of well known benchmark examples, BEATNP reduced CPU time by 1 to 3 orders of magnitude while retaining a significant majority of the optimization savings available in the unpartitioned case.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122503030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
NOISY: an electrical noise checker for ULSI noise:用于ULSI的电气噪声检测器
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122499
F. Gourdy, A. Greiner, M. Guillemet, R. Marbot, J. Murzin
{"title":"NOISY: an electrical noise checker for ULSI","authors":"F. Gourdy, A. Greiner, M. Guillemet, R. Marbot, J. Murzin","doi":"10.1109/ICCAD.1988.122499","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122499","url":null,"abstract":"NOISY is a part of an electrical rule checker with emphasis on noise computation. NOISY analyzes all types of noise, computes worst-case conditions using a relaxation algorithm, and draws a map of noise distribution in a chip. Its hierarchical organization allows verification of a high-complexity chip (more than 100000 transistors). Developed for CMOS circuitry, both static and dynamic, it can be extended to other types of technology.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131670922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Improved logic optimization using global flow analysis 改进的逻辑优化使用全局流分析
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122472
C. L. Berman, L. Trevillyan
{"title":"Improved logic optimization using global flow analysis","authors":"C. L. Berman, L. Trevillyan","doi":"10.1109/ICCAD.1988.122472","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122472","url":null,"abstract":"Techniques for automatically reducing circuit size and improving testability are considered. Two extensions to a previously published method for circuit optimization based on ideas of global flow analysis are described. The first is a basic improvement in the primary results on which the earlier optimization was based; the second extends the applicability of the method to conditional optimizations as well. Together these enhancements result in improved performance for the original algorithm, as well as the ability to handle designer-specified don't cares and redundancy-removal uniformly in the framework of a graph-based synthesis system such as LSS.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115484998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Logic simulation on vector processors 向量处理器的逻辑仿真
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122508
R. Raghavan, J. Hayes, W. Martin
{"title":"Logic simulation on vector processors","authors":"R. Raghavan, J. Hayes, W. Martin","doi":"10.1109/ICCAD.1988.122508","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122508","url":null,"abstract":"The performance of three commercial vector computers, the Cray X-MP/48, IBM 3090/400, and Alliant FX/8, for simulating logic circuits at gate level is compared. Experiments that assume zero- and unit-delay models demonstrate that certain key architectural features, especially, the presence of a scalar cache, have an adverse impact on the potential speedup. Consequently, the achievable speedup due to vectorization of simulation code, while still substantial, is less than expected. The results indicate that concurrent operation of multiple CPUs in vector mode in machines such as the Alliant FX/8 might be the most cost-effective speedup technique for logic simulation on current vector processors.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129109856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Aliasing probability of non-exhaustive randomized syndrome tests 非穷举随机综合征检验的混叠概率
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122500
R. Aitken, V. Agarwal
{"title":"Aliasing probability of non-exhaustive randomized syndrome tests","authors":"R. Aitken, V. Agarwal","doi":"10.1109/ICCAD.1988.122500","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122500","url":null,"abstract":"A comprehensive design methodology which includes built-in self-test (BIST) cannot be achieved without performance measures of BIST techniques. Exact and asymptotic expressions are derived for the aliasing probability of randomized syndrome testing using the independent error model proposed by T.W. Williams et al. (IEEE Trans. Computer-Aided Design, vol.7, no.1, p.75-83, 1988). It is shown that randomized syndrome testing outperforms signature analysis for a substantial class of functions, and that existing methods can be used to transform the remaining functions during test mode.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125390165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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