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[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers最新文献

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Parallel logic/fault simulation of VLSI array logic VLSI阵列逻辑的并行逻辑/故障仿真
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122491
P. Bose
{"title":"Parallel logic/fault simulation of VLSI array logic","authors":"P. Bose","doi":"10.1109/ICCAD.1988.122491","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122491","url":null,"abstract":"Current techniques in logic/fault simulation treat the problem as a nonnumeric one in which the basic primitives involved are Boolean operations, string matching/manipulation operations, bitwise or wordwise comparison operations, etc. A technique for reformulating the problem in terms of standard vector and matrix operation primitives which are well supported on all scientific machines is described. The overall computing environment is assumed to be a scientific/engineering one, with Fortran as the primary coding medium and the hardware biased toward numerically intensive applications. Attention is restricted to VLSI array logic.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134589224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulated annealing: a fast heuristic for some generic layout problems 模拟退火:一类通用布局问题的快速启发式算法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122560
Jimmy Lam, J. Delosme
{"title":"Simulated annealing: a fast heuristic for some generic layout problems","authors":"Jimmy Lam, J. Delosme","doi":"10.1109/ICCAD.1988.122560","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122560","url":null,"abstract":"It is shown that simulated annealing, with a properly designed annealing schedule and move-generation strategy, achieves significant speedups for high-quality solutions when compared with tailored heuristics on two well-studied problems: the traveling-salesman problem and the graph-partition problem. Efficient heuristics can be applied to power and ground routing for the traveling-salesman problem and to min-cut placement and logic partitioning for the graph-partition problem.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131031749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Timing optimization of combinational logic 组合逻辑的时序优化
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122511
K. J. Singh, Albert R. Wang, R. Brayton, A. Sangiovanni-Vincentelli
{"title":"Timing optimization of combinational logic","authors":"K. J. Singh, Albert R. Wang, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1988.122511","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122511","url":null,"abstract":"An algorithm for speeding up combinational logic with minimal area increase is presented. A static timing analyzer is used to identify the critical paths. Then a weighted min-cut algorithm is used to determine the subset of nodes to be resynthesized. This subset is selected so that the speedup is achieved with minimal area increase. Resynthesis is done by selectively collapsing the logic along the critical paths and then decomposing the collapsed nodes to minimize the critical delay. This process is iterated until either the timing requirements are satisfied or no further improvement can be made. The algorithm has been implemented and tested on many design examples with promising results.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131094949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 155
Constrained conditional resource sharing in pipeline synthesis 管道综合中约束条件资源共享
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122461
K. Hwang, A. Casavant, M. Dragomirecky, M. d'Abreu
{"title":"Constrained conditional resource sharing in pipeline synthesis","authors":"K. Hwang, A. Casavant, M. Dragomirecky, M. d'Abreu","doi":"10.1109/ICCAD.1988.122461","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122461","url":null,"abstract":"A conditional resource-sharing algorithm for pipeline synthesis is presented. It allows sharing of hardware components among the mutually exclusive parts of any conditional branches appearing in a behavioral description. If done improperly, resource sharing in a conditional branch can increase its critical path delay excessively, causing performance degradation. Given area/time constraints for a pipelined design, finding an optimal conditional sharing solution is a combinatorial optimization problem. The algorithm uses heuristics with a user-defined weight that trades off area versus time; the algorithm is either manually or automatically iterated by changing the weight until a solution close to the target is obtained or is determined to be impossible to obtain. The algorithm is interactive, so designers can manually determine partial or whole sharing.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132215604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A tabular macromodeling approach to fast timing simulation including parasitics 一种包含寄生的快速时序仿真的表格宏建模方法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122465
D. Overhauser, I. Hajj
{"title":"A tabular macromodeling approach to fast timing simulation including parasitics","authors":"D. Overhauser, I. Hajj","doi":"10.1109/ICCAD.1988.122465","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122465","url":null,"abstract":"The approach accounts for RC parasitic loading, overlapping inputs, and incomplete charging or discharging of output nodes. The macromodeling splits the subcircuits data into transistor-gate information and loading information. In a given design many subcircuits have identical gate configurations, but each instance of a gate has a unique RC loading condition. During simulation the gate and loading information is combined and used to calculate output-node voltage changes. All necessary information needed for voltage calculations are precomputed and stored in tables. The proposed macromodeling and the delay method greatly reduce simulation time. The approach has been implemented in a simulator called IDSIM2, and a number of large examples have been simulated. Speedups of up to three orders of magnitude have been obtained compared to standard circuit simulation, with loss of accuracy of less than 10%.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128696088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Delay computation in switch-level models of non-treelike MOS circuits 非树状MOS电路开关级模型的延迟计算
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122528
Denis Martin, N. Rumin
{"title":"Delay computation in switch-level models of non-treelike MOS circuits","authors":"Denis Martin, N. Rumin","doi":"10.1109/ICCAD.1988.122528","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122528","url":null,"abstract":"Various algorithmic and heuristic techniques are proposed for dealing with the problem of computing delays in switch-level models of MOS transistor circuits which contain loops. The nonlinear dependence of the effective channel resistance on the capacitive load is dealt with by adjusting the resistance within the iterative process of computing delay, using the Lin and Mead algorithm. Heuristics are proposed for reducing the number of iterations by splitting the loops at high capacitance nodes and by basing the initial values of the split capacitances on the path conductances. It is demonstrated that the decomposition of the transistor groups into bicomponents is very effective for large groups. Combinations of these techniques have been tested on a large variety of circuits, a representative subset of which is presented.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133679062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Test generation for sequential circuits using individual initial value propagation 使用单个初始值传播的顺序电路的测试生成
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122573
T. Ogihara, Shuichi Saruyama, S. Murai
{"title":"Test generation for sequential circuits using individual initial value propagation","authors":"T. Ogihara, Shuichi Saruyama, S. Murai","doi":"10.1109/ICCAD.1988.122573","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122573","url":null,"abstract":"Describes a test generation and fault simulation method which detects faults in the clock control logic that can cause register initialization failure in sequential circuits. By assigning an individual initial value X/sub n/ to the inaccessible register n in the faulty circuit and observing both the fault signal 0/X/sub n/ (0 in the good circuit/X/sub n/ in the faulty circuit) and 1/X/sub n/ in a different time frame, test vectors which can detect previously undetectable faults can be generated. Consequently, this method can generate test vectors with 98% to 100% fault coverage for sequential circuits for which conventional test generation methods only achieve 89% to 95% coverage.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133013940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Parallel polygon operations using loosely coupled workstations 使用松耦合工作站的并行多边形操作
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122510
Rod D. W. Widdowson, Kenny Ferguson
{"title":"Parallel polygon operations using loosely coupled workstations","authors":"Rod D. W. Widdowson, Kenny Ferguson","doi":"10.1109/ICCAD.1988.122510","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122510","url":null,"abstract":"Problems in two dimensions, such as the polygon operations which are performed on IC designs prior to fabrication, lend themselves well to functional distribution. The authors present a method for performing polygon operations in parallel which utilizes distributed workstations, obviating the need for performance improvement by special-purpose hardware. The method provides improved performance while remaining cost-effective and flexible. As designs become larger, more computers can be incorporated into the network. Results are presented for runs on collections of proprietary workstations.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125758094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Area-time model for synthesis of non-pipelined designs 非流水线设计综合的面积-时间模型
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122460
R. Jain, M. Mlinar, A. C. Parker
{"title":"Area-time model for synthesis of non-pipelined designs","authors":"R. Jain, M. Mlinar, A. C. Parker","doi":"10.1109/ICCAD.1988.122460","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122460","url":null,"abstract":"A mathematical model is presented for predicting the area-time tradeoff curve for nonpipelined data paths given a data-flow graph and a module set. Specifically, it examines operator cost and delay to predict the lower bound noninferior area-time curve. The model has been validated against designs generated by a program which synthesizes nonpipelined data paths.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124799124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
PLA optimization using output encoding 使用输出编码的PLA优化
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122553
A. Saldanha, R. Katz
{"title":"PLA optimization using output encoding","authors":"A. Saldanha, R. Katz","doi":"10.1109/ICCAD.1988.122553","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122553","url":null,"abstract":"An automatic tool that heuristically determines a good partitioning of a single large programmable logic array (PLA) into a PLA with a smaller number of encoded outputs (and usually fewer product terms), followed by a set of decoders to regenerate the original outputs, has been developed. Initial results using logic descriptions of processor chips and a benchmark set of industrial PLAs show area savings of up to 35% and delay reductions of up to 45%. The approach can be considered an alternative to Boolean decomposition and factoring in multilevel logic synthesis.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125910539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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