Test generation for sequential circuits using individual initial value propagation

Abstract

Describes a test generation and fault simulation method which detects faults in the clock control logic that can cause register initialization failure in sequential circuits. By assigning an individual initial value X/sub n/ to the inaccessible register n in the faulty circuit and observing both the fault signal 0/X/sub n/ (0 in the good circuit/X/sub n/ in the faulty circuit) and 1/X/sub n/ in a different time frame, test vectors which can detect previously undetectable faults can be generated. Consequently, this method can generate test vectors with 98% to 100% fault coverage for sequential circuits for which conventional test generation methods only achieve 89% to 95% coverage.<>