Delay computation in switch-level models of non-treelike MOS circuits

Abstract

Various algorithmic and heuristic techniques are proposed for dealing with the problem of computing delays in switch-level models of MOS transistor circuits which contain loops. The nonlinear dependence of the effective channel resistance on the capacitive load is dealt with by adjusting the resistance within the iterative process of computing delay, using the Lin and Mead algorithm. Heuristics are proposed for reducing the number of iterations by splitting the loops at high capacitance nodes and by basing the initial values of the split capacitances on the path conductances. It is demonstrated that the decomposition of the transistor groups into bicomponents is very effective for large groups. Combinations of these techniques have been tested on a large variety of circuits, a representative subset of which is presented.<>