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[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers最新文献

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A fault simulation method based on stem regions 基于主干区域的故障模拟方法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122487
F. Maamari, J. Rajski
{"title":"A fault simulation method based on stem regions","authors":"F. Maamari, J. Rajski","doi":"10.1109/ICCAD.1988.122487","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122487","url":null,"abstract":"The concept of stem regions has been used as a framework for a fast fault simulator for combinational circuits. The concept allows a static reduction of the circuit area of explicit analysis, for single-output as well as multiple-output circuits. A dynamic reduction of processing steps is also achieved as the fault simulation progresses and fault coverage increases. Both the static and dynamic reductions are fully compatible with the parallel pattern evaluation technique, resulting in a very efficient implementation. The simulation algorithm is described, and experimental results for well-known benchmark circuits are shown.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122246015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Hill climbing with reduced search space (logic optimization) 减少搜索空间的爬坡(逻辑优化)
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122514
D. Brand
{"title":"Hill climbing with reduced search space (logic optimization)","authors":"D. Brand","doi":"10.1109/ICCAD.1988.122514","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122514","url":null,"abstract":"A general optimization algorithm, which in some areas successfully competes with simulated annealing and the Kernighan-Lin algorithm, as well as special heuristics, is presented. It gains speed by taking advantage of the structure of the objective function in order to reduce the search space. Results obtained from the implementation of the algorithm on three problems are presented.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122994044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Evaluation and improvement of Boolean comparison method based on binary decision diagrams 基于二元决策图的布尔比较方法的评价与改进
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122450
M. Fujita, H. Fujisawa, N. Kawato
{"title":"Evaluation and improvement of Boolean comparison method based on binary decision diagrams","authors":"M. Fujita, H. Fujisawa, N. Kawato","doi":"10.1109/ICCAD.1988.122450","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122450","url":null,"abstract":"R.E. Bryant proposed a method to handle logic expressions (IEEE Trans. Comp., vol.25, no.8, p.667-91, 1986) which is based on binary decision diagrams (BDD) with restriction; variable ordering ix fixed throughout a diagram. The method is more efficient than other methods proposed so far and depends heavily on variable ordering. A simple but powerful algorithm for variable ordering is developed. The algorithm tries to find a variable ordering which minimizes the number of crosspoints of nets when the circuit diagram is drawn. This is applied to the Boolean comparison of ISCAS benchmark circuits for test pattern generation. The results show that binary decision diagrams (BDD) with the proposed ordering method can verify almost all benchmark circuits in less than several central processor unit (CPU) minutes, which is one hundred times (or more) faster than times reported in the literature. Some techniques for circuit evaluation ordering are also mentioned.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"190 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116349203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 252
Data parallel switch-level simulation 数据并行开关级仿真
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122527
R. Bryant
{"title":"Data parallel switch-level simulation","authors":"R. Bryant","doi":"10.1109/ICCAD.1988.122527","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122527","url":null,"abstract":"Data-parallel simulation involves simulating the behavior of a circuit over a number of test sequences simultaneously. Compared to other parallel simulation techniques, data-parallel simulation requires less overhead for synchronization and communication, and it permits higher degrees of parallelism. Two data-parallel versions of the switch-level simulator COSMOS have been implemented. The first runs on conventional machines, exploiting the bit parallelism of machine-level logic operations. This version runs 20-30 times faster than sequential simulation on the same machine. The second runs on a massively parallel SIMD machine, with each processor simulating the circuit behavior for a single test sequence. A simulator running on a 32768-processor machine runs up to 33000 times faster than a sequential simulator on a workstation computer.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128076602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Combining circuit level changes with electrical optimization 结合电路电平变化与电气优化
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122497
F. W. Obermeier, R. Katz
{"title":"Combining circuit level changes with electrical optimization","authors":"F. W. Obermeier, R. Katz","doi":"10.1109/ICCAD.1988.122497","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122497","url":null,"abstract":"A program, called EPOXY, which sizes a circuit's transistors to satisfy performance and area constraints is discussed. If these cannot be met, the program considers small circuit changes in an effort to meet the constraints. Several CMOS examples demonstrate how EPOXY applies these heuristics to meet difficult timing constraints, power requirements, and cell width and height limitations. Compact layout and aspect-ratio requirements are handled by a virtual grid area model. From an implementation viewpoint, EPOXY's underlying equation representation of circuit performance automatically provides critical path information and allows rapid modification of the circuit structure. When EPOXY was applied to a CMOS 16-bit adder, a speed improvement of 23% was achieved over transistor sizing alone while satisfying a height constraint. Similarly, the speed of a dynamic CMOS PLA was improved by 10% and that of an array of CMOS JK flip-flops by 23%.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126870333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Optimal CMOS cell transistor placement: a relaxation approach 最佳CMOS电池晶体管放置:一种松弛方法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122529
A. Stauffer, R. Nair
{"title":"Optimal CMOS cell transistor placement: a relaxation approach","authors":"A. Stauffer, R. Nair","doi":"10.1109/ICCAD.1988.122529","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122529","url":null,"abstract":"A relaxation approach for producing a placement of transistors in a CMOS cell in a grid layout style from the circuit schematic diagram is described. For a given objective function, the approach leads to optimal results in most of the cases attempted. Unlike previous constructive approaches, this approach is iterative. It is also quite flexible. It can be used for unrestricted circuit types and can handle a variety of other important parameters affecting the wireability of the layout. The procedure is targeted for use in the automatic generation of custom and gate-array cell libraries.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121884809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A method for net representation with polygon decomposition 一种基于多边形分解的网络表示方法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122498
C. Chi
{"title":"A method for net representation with polygon decomposition","authors":"C. Chi","doi":"10.1109/ICCAD.1988.122498","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122498","url":null,"abstract":"A method of decomposing polygons into convex subpolygons is presented. The result gives accurate polygon areas and maintains the tree-structure relationships of net branches represented by the polygon. Contacts which connect polygons on different layers are used. The whole net can be represented in a backward linklist. An implementation for treating signal delay in an RC tree network is discussed.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114964553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GeminiII: a second generation layout validation program GeminiII:第二代布局验证程序
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122520
C. Ebeling
{"title":"GeminiII: a second generation layout validation program","authors":"C. Ebeling","doi":"10.1109/ICCAD.1988.122520","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122520","url":null,"abstract":"Gemini is a program that is widely used to compare circuit layout against a specification. Extensions to Gemini that make it faster, enable it to isolate errors better, and extend its domain of application, are described. These improvements have been achieved by changes to the labeling algorithm, extensions to the local matching algorithm, better handling of symmetrical circuits, and the accommodation of series-connected transistors. GeminiII's algorithm is separated into global labeling and local matching phases. GeminiII dynamically switches between the two, depending on the amount of local structure contained in the circuit, taking advantage of the speed of the local matching algorithm when possible and relying on the power of the more general algorithm when the simple algorithm fails.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131047047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
CREST-a current estimator for CMOS circuits 用于CMOS电路的电流估计器
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122494
F. Najm, R. Burch, Ping Yang, I. Hajj
{"title":"CREST-a current estimator for CMOS circuits","authors":"F. Najm, R. Burch, Ping Yang, I. Hajj","doi":"10.1109/ICCAD.1988.122494","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122494","url":null,"abstract":"CREST is a pattern-independent current estimation approach developed to support electromigration analysis tools. It uses the powerful, original concept of probabilistic simulation to generate accurate estimates of the expected current waveforms efficiently. The original implementation of CREST is extended to circuits containing pass transistors, reconvergent fanout, and feedback, and heuristics to simulate circuits with large reconvergent fanout or feedback blocks efficiently are provided. The results of using CREST on several real circuits are presented.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133832780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Flexible module generation in the FACE design environment 在FACE设计环境下灵活的模块生成
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122536
William D. Smith, J. Jasica, M. Hartman, M. d'Abreu
{"title":"Flexible module generation in the FACE design environment","authors":"William D. Smith, J. Jasica, M. Hartman, M. d'Abreu","doi":"10.1109/ICCAD.1988.122536","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122536","url":null,"abstract":"The Flexible Architecture Compilation Environment (FACE) provides a common object-oriented representation for design information. A module-generation system built within the FACE environment that uses parameterized procedural module descriptions is discussed. These generators capture the knowledge of a designer and facilitate a high level of reuse of the modules and leaf cells. The system provides a general mechanism to parameterize design information and supports complex generators ranging from tiled structures to entire chips. This approach is applicable to many hardware architectures. Experience in the design of working VLSI chips is discussed.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132984969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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