{"title":"最佳CMOS电池晶体管放置:一种松弛方法","authors":"A. Stauffer, R. Nair","doi":"10.1109/ICCAD.1988.122529","DOIUrl":null,"url":null,"abstract":"A relaxation approach for producing a placement of transistors in a CMOS cell in a grid layout style from the circuit schematic diagram is described. For a given objective function, the approach leads to optimal results in most of the cases attempted. Unlike previous constructive approaches, this approach is iterative. It is also quite flexible. It can be used for unrestricted circuit types and can handle a variety of other important parameters affecting the wireability of the layout. The procedure is targeted for use in the automatic generation of custom and gate-array cell libraries.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"Optimal CMOS cell transistor placement: a relaxation approach\",\"authors\":\"A. Stauffer, R. Nair\",\"doi\":\"10.1109/ICCAD.1988.122529\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A relaxation approach for producing a placement of transistors in a CMOS cell in a grid layout style from the circuit schematic diagram is described. For a given objective function, the approach leads to optimal results in most of the cases attempted. Unlike previous constructive approaches, this approach is iterative. It is also quite flexible. It can be used for unrestricted circuit types and can handle a variety of other important parameters affecting the wireability of the layout. The procedure is targeted for use in the automatic generation of custom and gate-array cell libraries.<<ETX>>\",\"PeriodicalId\":285078,\"journal\":{\"name\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCAD.1988.122529\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.1988.122529","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimal CMOS cell transistor placement: a relaxation approach
A relaxation approach for producing a placement of transistors in a CMOS cell in a grid layout style from the circuit schematic diagram is described. For a given objective function, the approach leads to optimal results in most of the cases attempted. Unlike previous constructive approaches, this approach is iterative. It is also quite flexible. It can be used for unrestricted circuit types and can handle a variety of other important parameters affecting the wireability of the layout. The procedure is targeted for use in the automatic generation of custom and gate-array cell libraries.<>