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[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers最新文献

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Automatic test generation using neural networks 使用神经网络自动生成测试
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122540
S. Chakradhar, M. Bushnell, V. Agrawal
{"title":"Automatic test generation using neural networks","authors":"S. Chakradhar, M. Bushnell, V. Agrawal","doi":"10.1109/ICCAD.1988.122540","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122540","url":null,"abstract":"An automatic test pattern generation (ATPG) methodology that has the potential to exploit fine-grain parallel computing and relaxation techniques is described. The approach is radically different from the conventional methods used to generate tests for circuits from their gate-level descriptions. A digital circuit is represented as a bidirectional network of neurons. The circuit function is coded in the firing thresholds of neurons and the weights of interconnection links. This neural network is suitably reconfigured for solving the ATPG problem. A fault is injected into the neural network and an energy function is constructed with global minima at test vectors. Global minima are determined by a probabilistic relaxation technique augmented by a directed search. Preliminary results on combinational circuits confirm the feasibility of the technique.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126998330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Two-layer quad trees: a data structure for high-speed interactive layout tools 两层四叉树:用于高速交互式布局工具的数据结构
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122564
W. Li, Scott Legendre, Kevin Gardiner
{"title":"Two-layer quad trees: a data structure for high-speed interactive layout tools","authors":"W. Li, Scott Legendre, Kevin Gardiner","doi":"10.1109/ICCAD.1988.122564","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122564","url":null,"abstract":"A two-layer quad tree data structure which creates an effective search environment for both region queries and size queries is described. A corner-based sorting method resolves the quad tree bisector list problem. A region-growing technique reduces region query search overhead. A two-layer quad tree implementation improves size-query speed. Experimental results show that these techniques significantly improve query speed for both classes of queries.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131903883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
XPSim: a MOS VLSI simulator XPSim:一个MOS VLSI模拟器
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122464
Romy L. Bauer, Jiayuan Fang, Antony P.-C. Ng, Robert K. Brayton
{"title":"XPSim: a MOS VLSI simulator","authors":"Romy L. Bauer, Jiayuan Fang, Antony P.-C. Ng, Robert K. Brayton","doi":"10.1109/ICCAD.1988.122464","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122464","url":null,"abstract":"XPSim (formerly known as SuperCrystal), a multirate, event-driven circuit simulator suitable for large MOS VLSI circuits, is described. XPSim incorporates both static and dynamic partitioning of the circuit. Each partitioned subcircuit is numerically solved with a new integration method-the exponential function method. The voltage waveforms produced by this method are piecewise exponentials. Currently, XPSim supports up to a third-order explicit method. Preliminary tests indicate that XPSim exhibits a significant speedup over SPICE while retaining similar accuracy and is able to handle large circuits.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115086180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
CODECS: a fixed mixed-level device and circuit simulator CODECS:一个固定的混合电平设备和电路模拟器
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122474
K. Mayaram, D. Pederson
{"title":"CODECS: a fixed mixed-level device and circuit simulator","authors":"K. Mayaram, D. Pederson","doi":"10.1109/ICCAD.1988.122474","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122474","url":null,"abstract":"Mixed-level device and circuit simulation allows the use of one- or two-dimensional numerical models for critical devices in a circuit configuration. CODECS is a mixed-level device and circuit simulator that has been developed to support a variety of numerical models and analyses capabilities. Effective coupling of device and circuit simulation capabilities is achieved by a proper choice of algorithms and architecture. Several examples illustrate the advantages of CODECS for simulating both MOS and bipolar circuits.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114980384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Discrete-event simulation on hypercube architectures 超立方体结构上的离散事件仿真
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122509
R. Chamberlain, M. Franklin
{"title":"Discrete-event simulation on hypercube architectures","authors":"R. Chamberlain, M. Franklin","doi":"10.1109/ICCAD.1988.122509","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122509","url":null,"abstract":"A performance model for a hierarchical discrete-event-simulation algorithm running on a hypercube architecture is presented. A static allocation of system components to hypercube processors and a global clock algorithm with an event-based time increment are assumed. The model is applied to a digital systems simulation. The effects of different architectures, algorithm parameter values, and partitioning strategies on speedup are evaluated.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123447005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A modified approach to two-level logic minimization 一种改进的两级逻辑最小化方法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122473
A. A. Malik, R. Brayton, A. Newton, A. Sangiovanni-Vincentelli
{"title":"A modified approach to two-level logic minimization","authors":"A. A. Malik, R. Brayton, A. Newton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1988.122473","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122473","url":null,"abstract":"A methodology in which it is not necessary to compute the entire offset is presented, that still provides a global picture. This scheme has been implemented in ESPRESSO with an interface to the multilevel minimization environment MIS. Initial results show that for functions for which the ratio of the size of the cover to the size of the don't care set is small, the new approach is much faster. The initial interest was to use this mainly in a multilevel logic synthesis system where the desired don't care sets are typically large. Some results in this environment are given, and the new scheme is compared with ESPRESSO.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125059921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
GORDIAN: a new global optimization/rectangle dissection method for cell placement GORDIAN:一种新的单元格布局全局优化/矩形剖分方法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122559
J. M. Kleinhans, G. Sigl, F. Johannes
{"title":"GORDIAN: a new global optimization/rectangle dissection method for cell placement","authors":"J. M. Kleinhans, G. Sigl, F. Johannes","doi":"10.1109/ICCAD.1988.122559","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122559","url":null,"abstract":"A placement method for cell-based layout styles composed of alternating and interacting global optimization and partitioning phases is presented. In contrast to other methods using the divide-and-conquer paradigm, it maintains the simultaneous treatment of all cells during optimization over all levels of partitioning. In the global optimization phases, constrained quadratic optimization problems with unique global minima are solved. Their solutions induce the assignment of cells to regions during the partitioning phases. For general-cell circuits, a highly efficient exhaustive slicing procedure is applied to small subsets of cells. The designer may choose a configuration from a menu to meet his requirements on chip area, chip aspect ratio and wire length. Placements with high area utilization are obtained within short computation times. The method has been applied to general-cell and standard-cell circuits with up to 3000 cells and nets.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129805004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
An efficient compaction algorithm for test vectors of microprocessors and microcontrollers 微处理器和微控制器测试向量的有效压缩算法
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122532
R. K. Gulati, D. K. Goel
{"title":"An efficient compaction algorithm for test vectors of microprocessors and microcontrollers","authors":"R. K. Gulati, D. K. Goel","doi":"10.1109/ICCAD.1988.122532","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122532","url":null,"abstract":"A compaction algorithm is presented that takes advantage of the fact that repeating patterns in the simulation output of microprocessors and microcontrollers occur due to specific reasons. An instance of each different, multiply-occurring repeating pattern is extracted as a subroutine in an efficient manner, as compared to the ad hoc approaches used earlier. Compaction is then achieved by replacing the repeating patterns by calls to appropriate subroutines. The algorithm has been implemented in a C program, with excellent results obtained. A sample of the results is included.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121227108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Predictive subset testing for IC performance 集成电路性能预测子集测试
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122523
J. Brockman, S. W. Director
{"title":"Predictive subset testing for IC performance","authors":"J. Brockman, S. W. Director","doi":"10.1109/ICCAD.1988.122523","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122523","url":null,"abstract":"Predictive subset testing is based on a statistical model of parametric process variation. In this Monte Carlo approach, a statistical process simulation, coupled with circuit simulation, is used to determine the joint probability distribution of a set of circuit performances. By evaluating the joint probability distribution, rather than assuming the performances to be independent, correlations that exist between them can be exploited and the number of performances that need to be explicitly tested can be reduced. Once a subset of performances for explicit testing has been identified, regression models for the untested performances are constructed, and, from the confidence intervals, limits are assigned for the tested performances. In this manner, the values of the untested performances can be predicted, reducing test complexity and cost.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127776297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Logic verification using binary decision diagrams in a logic synthesis environment 在逻辑综合环境中使用二元决策图进行逻辑验证
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI: 10.1109/ICCAD.1988.122451
S. Malik, Albert R. Wang, R. Brayton, A. Sangiovanni-Vincentelli
{"title":"Logic verification using binary decision diagrams in a logic synthesis environment","authors":"S. Malik, Albert R. Wang, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.1988.122451","DOIUrl":"https://doi.org/10.1109/ICCAD.1988.122451","url":null,"abstract":"The results of a formal logic verification system implemented as part of the multilevel logic synthesis system MIS are discussed. Combinational logic verification involves checking two networks for functional equivalence. Techniques that flatten networks or use cube enumeration and simulation cannot be used with functions that have very large cube covers. Binary decision diagrams (BDDs) are canonical representations for Boolean functions and offer a technique for formal logic verification. However, the size of BDDs is sensitive to the variable ordering. Ordering strategies based on the network topology are considered. Using these strategies with BDDs, it has been possible to carry out formal verification for a larger set of networks than with existing verification systems. The present method proved significantly faster on the benchmark set of examples tested.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128935900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 517
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