An efficient compaction algorithm for test vectors of microprocessors and microcontrollers

Abstract

A compaction algorithm is presented that takes advantage of the fact that repeating patterns in the simulation output of microprocessors and microcontrollers occur due to specific reasons. An instance of each different, multiply-occurring repeating pattern is extracted as a subroutine in an efficient manner, as compared to the ad hoc approaches used earlier. Compaction is then achieved by replacing the repeating patterns by calls to appropriate subroutines. The algorithm has been implemented in a C program, with excellent results obtained. A sample of the results is included.<>