{"title":"超立方体结构上的离散事件仿真","authors":"R. Chamberlain, M. Franklin","doi":"10.1109/ICCAD.1988.122509","DOIUrl":null,"url":null,"abstract":"A performance model for a hierarchical discrete-event-simulation algorithm running on a hypercube architecture is presented. A static allocation of system components to hypercube processors and a global clock algorithm with an event-based time increment are assumed. The model is applied to a digital systems simulation. The effects of different architectures, algorithm parameter values, and partitioning strategies on speedup are evaluated.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Discrete-event simulation on hypercube architectures\",\"authors\":\"R. Chamberlain, M. Franklin\",\"doi\":\"10.1109/ICCAD.1988.122509\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A performance model for a hierarchical discrete-event-simulation algorithm running on a hypercube architecture is presented. A static allocation of system components to hypercube processors and a global clock algorithm with an event-based time increment are assumed. The model is applied to a digital systems simulation. The effects of different architectures, algorithm parameter values, and partitioning strategies on speedup are evaluated.<<ETX>>\",\"PeriodicalId\":285078,\"journal\":{\"name\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCAD.1988.122509\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.1988.122509","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Discrete-event simulation on hypercube architectures
A performance model for a hierarchical discrete-event-simulation algorithm running on a hypercube architecture is presented. A static allocation of system components to hypercube processors and a global clock algorithm with an event-based time increment are assumed. The model is applied to a digital systems simulation. The effects of different architectures, algorithm parameter values, and partitioning strategies on speedup are evaluated.<>