{"title":"GORDIAN:一种新的单元格布局全局优化/矩形剖分方法","authors":"J. M. Kleinhans, G. Sigl, F. Johannes","doi":"10.1109/ICCAD.1988.122559","DOIUrl":null,"url":null,"abstract":"A placement method for cell-based layout styles composed of alternating and interacting global optimization and partitioning phases is presented. In contrast to other methods using the divide-and-conquer paradigm, it maintains the simultaneous treatment of all cells during optimization over all levels of partitioning. In the global optimization phases, constrained quadratic optimization problems with unique global minima are solved. Their solutions induce the assignment of cells to regions during the partitioning phases. For general-cell circuits, a highly efficient exhaustive slicing procedure is applied to small subsets of cells. The designer may choose a configuration from a menu to meet his requirements on chip area, chip aspect ratio and wire length. Placements with high area utilization are obtained within short computation times. The method has been applied to general-cell and standard-cell circuits with up to 3000 cells and nets.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"59","resultStr":"{\"title\":\"GORDIAN: a new global optimization/rectangle dissection method for cell placement\",\"authors\":\"J. M. Kleinhans, G. Sigl, F. Johannes\",\"doi\":\"10.1109/ICCAD.1988.122559\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A placement method for cell-based layout styles composed of alternating and interacting global optimization and partitioning phases is presented. In contrast to other methods using the divide-and-conquer paradigm, it maintains the simultaneous treatment of all cells during optimization over all levels of partitioning. In the global optimization phases, constrained quadratic optimization problems with unique global minima are solved. Their solutions induce the assignment of cells to regions during the partitioning phases. For general-cell circuits, a highly efficient exhaustive slicing procedure is applied to small subsets of cells. The designer may choose a configuration from a menu to meet his requirements on chip area, chip aspect ratio and wire length. Placements with high area utilization are obtained within short computation times. The method has been applied to general-cell and standard-cell circuits with up to 3000 cells and nets.<<ETX>>\",\"PeriodicalId\":285078,\"journal\":{\"name\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"59\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCAD.1988.122559\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.1988.122559","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
GORDIAN: a new global optimization/rectangle dissection method for cell placement
A placement method for cell-based layout styles composed of alternating and interacting global optimization and partitioning phases is presented. In contrast to other methods using the divide-and-conquer paradigm, it maintains the simultaneous treatment of all cells during optimization over all levels of partitioning. In the global optimization phases, constrained quadratic optimization problems with unique global minima are solved. Their solutions induce the assignment of cells to regions during the partitioning phases. For general-cell circuits, a highly efficient exhaustive slicing procedure is applied to small subsets of cells. The designer may choose a configuration from a menu to meet his requirements on chip area, chip aspect ratio and wire length. Placements with high area utilization are obtained within short computation times. The method has been applied to general-cell and standard-cell circuits with up to 3000 cells and nets.<>