Parallel logic/fault simulation of VLSI array logic

Abstract

Current techniques in logic/fault simulation treat the problem as a nonnumeric one in which the basic primitives involved are Boolean operations, string matching/manipulation operations, bitwise or wordwise comparison operations, etc. A technique for reformulating the problem in terms of standard vector and matrix operation primitives which are well supported on all scientific machines is described. The overall computing environment is assumed to be a scientific/engineering one, with Fortran as the primary coding medium and the hardware biased toward numerically intensive applications. Attention is restricted to VLSI array logic.<>