CLAY:一种用于CMOS布局合成的可延展单元多单元晶体管矩阵方法

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers Pub Date : 1988-11-07 DOI:10.1109/ICCAD.1988.122481

P. Kollaritsch, S. Lusky, S. Prasad, Neil Potter

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引用次数: 8

摘要

CLAY需要一个划分到晶体管级的网表，一个具有任意数量金属层的技术文件，以及对方面和I/O信号位置的限制来产生掩模几何形状。CLAY试图在软件中捕获晶体管级别(允许可变形状的单元，包括高度)和VLSI尺寸示例的平面图级别的布局知识。CLAY与标准细胞和手动方法相比效果更好。

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CLAY: a malleable-cell multi-cell transistor matrix approach for CMOS LAYout synthesis

CLAY takes a netlist partitioned down to the transistor level, a technology file with an arbitrary number of metal layers, and constraints on aspect and I/O signal positions to produce mask geometries. CLAY attempts to capture, in software, layout knowledge at the transistor level (allowing variable-shaped cells including heights) and at the floorplan level for VLSI sized examples. CLAY compares well with standard cell and manual approaches.<>

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来源期刊

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers

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