Input assignment algorithm for decoded-PLAs with multi-input decoders

Kuang-Chien Chen, S. Muroga
{"title":"Input assignment algorithm for decoded-PLAs with multi-input decoders","authors":"Kuang-Chien Chen, S. Muroga","doi":"10.1109/ICCAD.1988.122552","DOIUrl":null,"url":null,"abstract":"A heuristic algorithm for assigning input variables to the decoders of a decoded-programmable logic array (PLA) is presented. In this algorithm, the number of inputs to each decoder is not restricted to two and the area overhead incurred by using multi-input decoders is considered in the cost function. Experimental results show that the areas of multi-input decoded-PLAs designed by this algorithm are smaller in many cases than those of decoded-PLAs with two-input decoders or standard PLAs.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.1988.122552","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12

Abstract

A heuristic algorithm for assigning input variables to the decoders of a decoded-programmable logic array (PLA) is presented. In this algorithm, the number of inputs to each decoder is not restricted to two and the area overhead incurred by using multi-input decoders is considered in the cost function. Experimental results show that the areas of multi-input decoded-PLAs designed by this algorithm are smaller in many cases than those of decoded-PLAs with two-input decoders or standard PLAs.<>
带多输入解码器的译码pla输入分配算法
提出了一种为可编程序逻辑阵列(PLA)解码器分配输入变量的启发式算法。在该算法中,每个解码器的输入数不限制为两个,并且在代价函数中考虑了使用多输入解码器所产生的面积开销。实验结果表明,在许多情况下,该算法设计的多输入译码电路比双输入译码电路或标准译码电路的译码电路面积小
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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