{"title":"一个新的基于行布局的全局路由器","authors":"Kai-Win Lee, C. Sechen","doi":"10.1109/ICCAD.1988.122489","DOIUrl":null,"url":null,"abstract":"A global router for row-based layout styles such as sea-of-gates, gate-array, and standard cell circuits is discussed. It is part of the latest version of TimberWolfSC, a placement and routing package for row-based layout. The algorithm outperformed the UTMC Highland system on two standard benchmark circuits. In tests on ten circuits, the global router produced track counts which were an average of 27% lower than those of the previous TimberWolfSC global router. The router is an average of 30 times faster than the previous algorithm. It has been generalized to handle macro blocks on the chip, equivalent sets of pins, single pins (those without an equivalent), and circuits having many or no built-into-the-cell feeds. Indiscriminate over-the-cell routing is also handled.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"89","resultStr":"{\"title\":\"A new global router for row-based layout\",\"authors\":\"Kai-Win Lee, C. Sechen\",\"doi\":\"10.1109/ICCAD.1988.122489\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A global router for row-based layout styles such as sea-of-gates, gate-array, and standard cell circuits is discussed. It is part of the latest version of TimberWolfSC, a placement and routing package for row-based layout. The algorithm outperformed the UTMC Highland system on two standard benchmark circuits. In tests on ten circuits, the global router produced track counts which were an average of 27% lower than those of the previous TimberWolfSC global router. The router is an average of 30 times faster than the previous algorithm. It has been generalized to handle macro blocks on the chip, equivalent sets of pins, single pins (those without an equivalent), and circuits having many or no built-into-the-cell feeds. Indiscriminate over-the-cell routing is also handled.<<ETX>>\",\"PeriodicalId\":285078,\"journal\":{\"name\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"89\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCAD.1988.122489\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.1988.122489","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A global router for row-based layout styles such as sea-of-gates, gate-array, and standard cell circuits is discussed. It is part of the latest version of TimberWolfSC, a placement and routing package for row-based layout. The algorithm outperformed the UTMC Highland system on two standard benchmark circuits. In tests on ten circuits, the global router produced track counts which were an average of 27% lower than those of the previous TimberWolfSC global router. The router is an average of 30 times faster than the previous algorithm. It has been generalized to handle macro blocks on the chip, equivalent sets of pins, single pins (those without an equivalent), and circuits having many or no built-into-the-cell feeds. Indiscriminate over-the-cell routing is also handled.<>