{"title":"iPRIDE:使用直接方法的并行集成电路模拟器","authors":"Mi-Chang Chang, I. Hajj","doi":"10.1109/ICCAD.1988.122516","DOIUrl":null,"url":null,"abstract":"A parallel circuit simulator, iPRIDE, which uses a direct solution method and runs on a shared-memory multiprocessor is described. The simulator is based on a multilevel node tearing approach which produces a nested bordered-block-diagonal (BBD) form of the circuit equation matrix. The parallel solution of the nested BBD matrix is described. Its efficiency is shown to depend on how the circuit is partitioned as well as the sequence in which the concurrent tasks (scheduling) are solved. A partitioning heuristic is proposed, assuming that an arbitrary number of processors is available. Scheduling methods are studied when the number of processors is fixed. A method for determining the optimal level of partitioning, which depends on the number of processors as well as the scheduling methods, is described. The program is implemented on an ALLIANT FX/8 multiprocessor with shared memory. The performance of the program is reported.<<ETX>>","PeriodicalId":285078,"journal":{"name":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"iPRIDE: a parallel integrated circuit simulator using direct method\",\"authors\":\"Mi-Chang Chang, I. Hajj\",\"doi\":\"10.1109/ICCAD.1988.122516\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A parallel circuit simulator, iPRIDE, which uses a direct solution method and runs on a shared-memory multiprocessor is described. The simulator is based on a multilevel node tearing approach which produces a nested bordered-block-diagonal (BBD) form of the circuit equation matrix. The parallel solution of the nested BBD matrix is described. Its efficiency is shown to depend on how the circuit is partitioned as well as the sequence in which the concurrent tasks (scheduling) are solved. A partitioning heuristic is proposed, assuming that an arbitrary number of processors is available. Scheduling methods are studied when the number of processors is fixed. A method for determining the optimal level of partitioning, which depends on the number of processors as well as the scheduling methods, is described. The program is implemented on an ALLIANT FX/8 multiprocessor with shared memory. The performance of the program is reported.<<ETX>>\",\"PeriodicalId\":285078,\"journal\":{\"name\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCAD.1988.122516\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.1988.122516","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
iPRIDE: a parallel integrated circuit simulator using direct method
A parallel circuit simulator, iPRIDE, which uses a direct solution method and runs on a shared-memory multiprocessor is described. The simulator is based on a multilevel node tearing approach which produces a nested bordered-block-diagonal (BBD) form of the circuit equation matrix. The parallel solution of the nested BBD matrix is described. Its efficiency is shown to depend on how the circuit is partitioned as well as the sequence in which the concurrent tasks (scheduling) are solved. A partitioning heuristic is proposed, assuming that an arbitrary number of processors is available. Scheduling methods are studied when the number of processors is fixed. A method for determining the optimal level of partitioning, which depends on the number of processors as well as the scheduling methods, is described. The program is implemented on an ALLIANT FX/8 multiprocessor with shared memory. The performance of the program is reported.<>