Automatic layout of custom analog cells in ANAGRAM

Abstract

ANAGRAM models cell layout in the style of a macrocell place-and-route problem. Individual cell primitives (transistor-level objects of widely varying sizes) are the macrocells. Module generation techniques are used to generate these internal primitives and to preserve critical matching and symmetries. An annealing-based placement algorithm then places these primitives. This is followed by a novel line-expansion signal router, which includes mechanisms to avoid noise coupling due to internodal capacitances between the signal wires and shared parasitic resistances in the DC supply wiring and operates in an iterative improvement fashion to eliminate such violations. Layouts for several custom CMOS cells have been successfully generated. Circuit-simulation results based on cell extractions demonstrate the effectiveness of the crosstalk-avoidance mechanisms.<>