iEDISON: an interactive statistical design tool for MOS VLSI circuits

Abstract

iEDISON optimizes the transistor sizes of a circuit so that its performance is least sensitive to manufacturing process fluctuations. iEDISON considers three methods for design optimization, namely, the response surface method, the Taguchi method, and the nonnested experimental design method. These methods use experimental designs and regression models to explore the statistical performance variations. The efficiency of the system is demonstrated by an example on clock-skew minimization.<>