{"title":"The effect of defect clustering on test transparency and defect levels","authors":"A. Singh, C. M. Krishna","doi":"10.1109/VTEST.1993.313301","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313301","url":null,"abstract":"Proposes a wafer based testing approach which for the first time employs defect clustering information on the wafer to optimize test cost and defect levels in the shipped product. Preliminary analysis of this approach had assumed that the probability that a test detects a faulty circuit is independent of the number of faulty dies in the neighborhood of the circuit under test. Here, the authors relax this assumption by making test transparency a function of the number of faults. In this paper they study the effect of clustering on test transparency and defect levels based on maps of particle distributions on test wafers.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133033750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Classification of bridging faults in CMOS circuits: experimental results and implications for test","authors":"S. Midkiff, S. Bollinger","doi":"10.1109/VTEST.1993.313298","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313298","url":null,"abstract":"Investigates linkages between physically realistic faults in CMOS integrated circuits and test generation and test quality. The procedure and results for an inductive fault analysis experiment that determined likely bridging faults in a set of CMOS circuits are presented. The implications of the results on test generation for physically realistic faults and on fault coverage are discussed.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114451478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On the design for testability of sequential circuits","authors":"Xiao Sun, F. Lombardi","doi":"10.1109/VTEST.1993.313334","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313334","url":null,"abstract":"Presents a new approach for design-for-testability (DFT) of sequential circuits. The proposed approach is based on augmenting the system under test (SUT) with additional circuitry such that the combinational part of the SUT and the sequential part (i.e. the flip-flops) can be tested independently (disjoint testing).<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133536163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Error detection, fault location and reconfiguration for 2D mesh processing element arrays for digital signal processing","authors":"Guoning Liao","doi":"10.1109/VTEST.1993.313308","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313308","url":null,"abstract":"Presents a new and efficient error detection and fault location technique suitable for high performance application specific processing element (PE) arrays. In the proposed scheme, two spare PEs are located within four PEs, which forms a reconfigurable fault-tolerant module (RFTM). Any spare can functionally replace any one of the primary PEs within the RTFM. Since spares are physically close to the PEs that they replace, reconfiguration interconnections are short, thus minimizing the performance degradation. The new fault tolerant structure, RFTM, not only provides error detection mechanism, but also achieves fault tolerance. The authors have developed an error detection and fault location algorithm for the RFTM, which makes use of the information that is only available in a fault tolerant structure, but not available in other local redundancy techniques. Then, a systematic way of fault isolation was presented. A major contribution of this paper is that the authors approached the error detection, fault location and fault isolation in a unified way within the RFTM. The simple error detection and fault location mechanism turned out to result in a lean implementation of RFTM.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126359617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Computer-aided failure analysis of VLSI circuits using I/sub DDQ/ testing","authors":"Samir B. Naik, Wojciech Maly","doi":"10.1109/VTEST.1993.313300","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313300","url":null,"abstract":"A new approach to IC diagnosis, based on realistic defect modelling, has been recently proposed. Algorithms have been devised to generate 'good' diagnostic test sets. In this paper, the authors demonstrate that high levels of diagnostic resolution can be obtained for CMOS random logic, especially when abnormal I/sub DDQ/ current measurements are monitored in addition to circuit output voltages.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131479038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Defect-tolerant cache memory design","authors":"Dan Lamet, J. Frenzel","doi":"10.1109/VTEST.1993.313331","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313331","url":null,"abstract":"The design of a defect-tolerant control circuit for a set-associative cache memory is presented. The circuit maintains the stack ordering necessary for implementing the LRU replacement algorithm. A discussion of programming techniques for bypassing defective blocks is included.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117011588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"LFSR based deterministic hardware for at-speed BIST","authors":"B. Vasudevan, D. Ross, M. Gala, K. Watson","doi":"10.1109/VTEST.1993.313323","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313323","url":null,"abstract":"A deterministic test pattern generator for BIST, based on linear feedback shift registers is discussed. A method of designing the test pattern generator in order that it generates deterministic as well as pseudo random patterns is presented. One application of this method is illustrated where deterministic at-speed testing of C-testable ILAs, covering all possible single and multiple combinational faults is achieved. Response analysers are discussed including one with zero aliasing probability. The algorithms for synthesizing the small amount of BIST hardware are explained.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123409701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A distributed BIST control scheme for complex VLSI devices","authors":"Y. Zorian","doi":"10.1109/VTEST.1993.313316","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313316","url":null,"abstract":"BIST is a viable approach to test today's digital systems. Constraints, such as power, noise, area overhead, and others, limit the possibilities of parallel BIST execution in complex VLSI devices. This paper presents a BIST scheduling process that takes into consideration such constraints, and introduces a new BIST control methodology, that implements the BIST schedule with a highly modular architecture. In fact, due to the uniformity of interface, the BIST control elements are independent of the BIST scheme used in the embedded blocks of a device. This BIST control architecture can provide block level diagnostic information.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128379113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On the check base selection problem for fast adders","authors":"U. Sparmann","doi":"10.1109/VTEST.1993.313307","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313307","url":null,"abstract":"Considers the problem of selecting a suitable check base for on-line error detection by residue codes in fast adders. The dependency between structural properties of an adder and its set of possible error values is characterized. Based on this characterization an efficient procedure is developed for testing the appropriateness of a check base for a specific adder.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126689425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evaluation of test generation algorithms","authors":"Y. Min, Zhongcheng Li","doi":"10.1109/VTEST.1993.313376","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313376","url":null,"abstract":"Many ATPG algorithms are proposed every year. Evaluation of ATPG algorithms not only provides possibility to compare algorithms, but also predicts required computation resources for design and test of extra large circuits. The evaluation includes aspects of fault coverage, computation efficiency, and test set size. ISCAS 85 and ISCAS 89 benchmark circuits are available common examples for the evaluation. This paper presents a general methodology for the evaluation in spite of the difference of the computing environments that the algorithms run in. Eleven ATPG algorithms are evaluated, as a case study, based on the data of their experimental results published in the literature to show the feasibility and validation of the methodology presented.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128183527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}