Santa Cruz, Alvin Lun-Knep, Jee, F. Ferguson, Kevin Karplus, T. Larrabee
{"title":"Carafe: an inductive fault analysis tool for CMOS VLSI circuits","authors":"Santa Cruz, Alvin Lun-Knep, Jee, F. Ferguson, Kevin Karplus, T. Larrabee","doi":"10.1109/VTEST.1993.313302","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313302","url":null,"abstract":"Traditional fault models for testing CMOS VLSI circuits do not take into account the actual mechanisms that precipitate faults in CMOS circuits. As a result, tests based on traditional fault models may not detect all the faults that occur in the circuit. This paper discusses the Carafe software package which determines which faults are likely to occur in a circuit based on the circuit's physical design, defect parameters, and fabrication technology.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114960480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Dunn, D. Balazich, Lawrence K. Lange, Charlotte C. Montillo
{"title":"Pattern generator card, emulation, and debug","authors":"S. Dunn, D. Balazich, Lawrence K. Lange, Charlotte C. Montillo","doi":"10.1109/VTEST.1993.313379","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313379","url":null,"abstract":"Details a pattern generator card used in a high speed VLSI test system, a software emulation of that card, and card debug procedure. The Advanced Test System built at IBM East Fishkill contains primarily pin electronics cards, pattern generator cards, and power and clock distribution cards. The software emulator, called PGEM, for pattern generator emulation, serves two major purposes: it facilitates off-line debug of pattern generator cards; and, when used with a waveform tool, it permits verification of test programs without wasting system time. The simplification of off-line debug is important in terms of time savings and reduction of expensive incorrect diagnoses.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126376659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Aliasing-free error detection (ALFRED)","authors":"K. Chakrabarty, J. Hayes","doi":"10.1109/VTEST.1993.313356","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313356","url":null,"abstract":"Aliasing, which is the mapping of a faulty circuit's signature onto the fault-free signature, is a major problem in signature analysis. The authors present a new design technique (ALFRED) for zero aliasing based on the concept of sequence detection. For a test sequence of length n, the length of the signature in ALFRED is Theta (log n). The authors reduce the circuit complexity by adopting a shift-register-like structure that minimizes the logical dependencies of all but one of the flip-flops. They relate the theory of balanced functions to ALFRED, and demonstrate the feasibility of the approach by using it to design a signature analyzer for a carry-lookahead adder.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128803429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault injection scan design for enhanced VLSI design verification","authors":"S. Chau","doi":"10.1109/VTEST.1993.313299","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313299","url":null,"abstract":"Proposes a design technique called the fault injection scan register (FISR) for fault injection that has much higher fault coverage than the traditional pin-level fault injection for systems using complex VLSI components. The FISR utilizes the scan-in-scan-out design inject faults to the internal circuits of a VLSI chip. The fault injection is accomplished by loading a pair of fault vectors to a set of fault latches via the scan registers. The fault latches are then enabled so that the target signals will be forced to high or low during the normal operation. the delivery of injected faults via the scan registers and the concept of fault vector are the major innovations in the design. An innovative three stage flip-flop is also used to reduce the implementation overhead of the FISR.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116755470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Parallelization methods for circuit partitioning based parallel automatic test pattern generation","authors":"R. Klenke, Ronald D. Williams, J. Aylor","doi":"10.1109/VTEST.1993.313305","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313305","url":null,"abstract":"Generation of test vectors for the VLSI devices used in contemporary digital systems is becoming much more difficult as these devices increase in size. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Parallel processing techniques can be applied to accelerate the process of finding test patterns. One problem with this approach is that most currently available distributed memory multicomputers have a limited amount of memory on each processor which limits the size of the circuit database that can be contained on a single node. Topological partitioning of the circuit database across several processors can increase the size of VLSI circuits that can be processed on a given parallel machine. This paper presents the architecture of a topologically partitioned ATPG system and several partitioning algorithms that can be used to partition the circuit-under-test. This paper also presents several parallelization methods that may be applied to topologically partitioned ATPG on a distributed memory multicomputer. Results of using these parallelization techniques along with topological partitioning are presented.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131346151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Contactless characterization of microwave integrated circuits by device internal indirect electro-optic probing","authors":"F. Taenzler, T. Novak, E. Kubalek","doi":"10.1109/VTEST.1993.313296","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313296","url":null,"abstract":"Deals with a contactless working test system for the internal test of monolithic microwave integrated circuits (MMIC) based on both: III-V-semiconductor and Si-substrate material. This electro-optic test system determines the electrical field above the test-point within the MMIC. Measurements demonstrate the capability of this test system for device internal function control and failure analysis.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131891810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A structured design for test methodology","authors":"Kumar Venkat","doi":"10.1109/VTEST.1993.313372","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313372","url":null,"abstract":"Presents a case study of a structured design for test (DFT) methodology that was formulated for a major system design project consisting of 11 complex ASICs. The methodology includes full scan for chip test, and an optimized boundary scan for board test. The paper discusses details of the ASIC designs and technology, the DFT methodology, the design of test logic, ATPG tool selection, development of in-house tools, and integration of DFT into the overall design flow. This project has demonstrated that DFT can be considered early in the design and integrated efficiently into the design flow.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124461156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On diagnosis of faults in a scan-chain","authors":"S. Kundu","doi":"10.1109/VTEST.1993.313363","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313363","url":null,"abstract":"Testing screens for good chips. However, when test fall out is high (low yield) it becomes necessary to diagnose faults so that the manufacturing process or physical design can be fixed to improve yield. Several scan based diagnostic schemes are used in industry. They work when the scan chain itself is fault free. This paper describes a diagnosis system that can diagnose faults in a scan chain.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129172808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact of high level functional constraints on testability","authors":"Jaushin Lee, V. Chickermane, J. Patel","doi":"10.1109/VTEST.1993.313364","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313364","url":null,"abstract":"When a logic module is embedded in a large circuit, the architectural level functional constraints usually cause don't cares at the interface of this module. If the logic of the module is not synthesized using these don't cares, then redundancy may exist making the circuit very hard to test. In this paper, architectural level circuit structural and instruction behavioral information is exploited to analyze functional constraints and extract don't cares. The don't cares are used to optimize the logic of the module and to remove many redundant faults.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115598870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Estimation of reject ratio in testing of combinatorial circuits","authors":"D. Gaitonde, J. Khare, D. Walker, Wojciech Maly","doi":"10.1109/VTEST.1993.313370","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313370","url":null,"abstract":"Estimating the reject ratio for integrated circuits is an important problem to a test engineer. Using information about the decrease in reject ratio with increasing test length, the test engineer can estimate the test length necessary to achieve a desired product quality goal. This paper suggests a method for estimation of reject ratio for random testing of combinatorial circuits that takes into account differing individual fault probabilities. The authors also suggest some ways of estimating the fault probabilities. They then demonstrate the method on an example and compare results to previous work.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"40 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130350352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}