Estimation of reject ratio in testing of combinatorial circuits

D. Gaitonde, J. Khare, D. Walker, Wojciech Maly
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引用次数: 6

Abstract

Estimating the reject ratio for integrated circuits is an important problem to a test engineer. Using information about the decrease in reject ratio with increasing test length, the test engineer can estimate the test length necessary to achieve a desired product quality goal. This paper suggests a method for estimation of reject ratio for random testing of combinatorial circuits that takes into account differing individual fault probabilities. The authors also suggest some ways of estimating the fault probabilities. They then demonstrate the method on an example and compare results to previous work.<>
组合电路测试中拒绝率的估计
集成电路的抑制比估计是测试工程师面临的一个重要问题。利用有关随着测试长度的增加而降低废品率的信息,测试工程师可以估计达到期望的产品质量目标所需的测试长度。提出了一种考虑不同个体故障概率的组合电路随机测试拒绝率估计方法。作者还提出了一些估计故障概率的方法。然后,他们在一个例子上演示了该方法,并将结果与之前的工作进行了比较
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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