容错缓存存储器设计

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI:10.1109/VTEST.1993.313331

Dan Lamet, J. Frenzel

{"title":"容错缓存存储器设计","authors":"Dan Lamet, J. Frenzel","doi":"10.1109/VTEST.1993.313331","DOIUrl":null,"url":null,"abstract":"The design of a defect-tolerant control circuit for a set-associative cache memory is presented. The circuit maintains the stack ordering necessary for implementing the LRU replacement algorithm. A discussion of programming techniques for bypassing defective blocks is included.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Defect-tolerant cache memory design\",\"authors\":\"Dan Lamet, J. Frenzel\",\"doi\":\"10.1109/VTEST.1993.313331\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of a defect-tolerant control circuit for a set-associative cache memory is presented. The circuit maintains the stack ordering necessary for implementing the LRU replacement algorithm. A discussion of programming techniques for bypassing defective blocks is included.<<ETX>>\",\"PeriodicalId\":283218,\"journal\":{\"name\":\"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium\",\"volume\":\"61 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-04-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1993.313331\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1993.313331","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

提出了一种集关联缓存容错控制电路的设计方法。电路维持实现LRU替换算法所必需的堆栈顺序。对绕过有缺陷块的编程技术的讨论也包括在内

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Defect-tolerant cache memory design

The design of a defect-tolerant control circuit for a set-associative cache memory is presented. The circuit maintains the stack ordering necessary for implementing the LRU replacement algorithm. A discussion of programming techniques for bypassing defective blocks is included.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium

自引率

0.00%

发文量