On the design for testability of sequential circuits

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI:10.1109/VTEST.1993.313334

Xiao Sun, F. Lombardi

引用次数: 2

Abstract

Presents a new approach for design-for-testability (DFT) of sequential circuits. The proposed approach is based on augmenting the system under test (SUT) with additional circuitry such that the combinational part of the SUT and the sequential part (i.e. the flip-flops) can be tested independently (disjoint testing).<>

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顺序电路的可测试性设计

提出了一种时序电路可测试性设计(DFT)的新方法。所提出的方法是基于用额外的电路来增强被测系统(SUT)，这样SUT的组合部分和顺序部分(即触发器)可以独立测试(不连接测试)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium

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