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Reverse polarity protection for automotive NMOS LDO 汽车NMOS LDO反极性保护
2021 International Semiconductor Conference (CAS) Pub Date : 2021-10-06 DOI: 10.1109/CAS52836.2021.9604200
P. Pop, Gabriel Petrasuc, C. Pleşa, M. Neag, T. Salajan
{"title":"Reverse polarity protection for automotive NMOS LDO","authors":"P. Pop, Gabriel Petrasuc, C. Pleşa, M. Neag, T. Salajan","doi":"10.1109/CAS52836.2021.9604200","DOIUrl":"https://doi.org/10.1109/CAS52836.2021.9604200","url":null,"abstract":"ICs designed for automotive applications should withstand accidental reverse polarity caused by misconnection of their supply lines to the car battery. The reverse protection circuitry should avoid damages to both the IC and the system the IC is connected to. In particular, a large power dissipation while in reverse polarity situation is to be avoided. A simple solution is to insert diodes between the supply lines and the IC supply pins but this cannot be applied to linear low dropout regulators (LDOs)This paper presents two reverse polarity protection solutions for LDOs with NMOS power transistors. Starting from a circuit based on bipolar transistors, the proposed solutions can be implemented in low-cost CMOS processes. One of them also requires far less die-area Simulation results presented in the paper validate both proposals.","PeriodicalId":281480,"journal":{"name":"2021 International Semiconductor Conference (CAS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132060469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improving the On-Current of Junctionless Carbon Nanotube Tunneling FETs Using a Heavily n-Type Doped Pocket 利用重n型掺杂袋提高无结碳纳米管隧道场效应管的导通电流
2021 International Semiconductor Conference (CAS) Pub Date : 2021-10-06 DOI: 10.1109/CAS52836.2021.9604136
K. Tamersit
{"title":"Improving the On-Current of Junctionless Carbon Nanotube Tunneling FETs Using a Heavily n-Type Doped Pocket","authors":"K. Tamersit","doi":"10.1109/CAS52836.2021.9604136","DOIUrl":"https://doi.org/10.1109/CAS52836.2021.9604136","url":null,"abstract":"In this paper, the on-current of the junctionless carbon nanotube tunnel field-effect transistor is improved using a simple approach based on the use of a heavily n-type doped pocket. This latter is incorporated in the carbon nanotube channel between the auxiliary p-type gate and the control gate. The proposed technique is verified computationally via a quantum simulation approach that solves the computational couple including the Poisson equation solver and the non-equilibrium Green’s function solver. The mode space representation and the ballistic transport conditions are considered. It has been found that the proposed technique is efficient in improving the on-current, off-current, current ratio, subthreshold swing, while keeping the junctionless aspect. In addition, the recorded improvements have been deeply investigated using the relevant band diagrams. The obtained results make the proposed approach as a promising and alternative method, which can be applied to boost other junctionless TFET endowed with auxiliary and the control gates.","PeriodicalId":281480,"journal":{"name":"2021 International Semiconductor Conference (CAS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132331282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Numerical Modelling of 180° Hybrid Ring Couplers Operating in the GSM 1800 Band 在GSM 1800波段工作的180°混合环形耦合器的数值模拟
2021 International Semiconductor Conference (CAS) Pub Date : 2021-10-06 DOI: 10.1109/CAS52836.2021.9604117
V. Ionescu
{"title":"Numerical Modelling of 180° Hybrid Ring Couplers Operating in the GSM 1800 Band","authors":"V. Ionescu","doi":"10.1109/CAS52836.2021.9604117","DOIUrl":"https://doi.org/10.1109/CAS52836.2021.9604117","url":null,"abstract":"This numerical study is developed with Ansys HFSS software to evaluate the performance of ten conventional rat-race coupler models at a centre frequency of 1.85 GHz by using FR4, Duroid 5880, Duroid 6006 and TMM4 substrate types. We investigated the combined effect of the dielectric constant, dielectric loss tangent and substrate thickness upon the S-parameters variation. Duroid 5880 substrate with thickness of 0.79 mm, dielectric constant of 2.2 and loss tangent of 0.0009 had the lowest dielectric loss, lowest propagation delay time and the highest Q–factor. The coupler model based on this substrate presented the lowest deviation from the desired – 3dB value for the insertion loss coefficients and the highest isolation value at 1.85 GHz. The phase imbalance between signals at the output ports was also close to the desired value of 180% for this Duroid 5880 based model. This phase difference value was about 0.2° higher than the value attained for the model with FR4 substrate.","PeriodicalId":281480,"journal":{"name":"2021 International Semiconductor Conference (CAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127458010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Superior Interface Trap Variability Immunity of Horizontally Stacked Si Nanosheet FET in Sub-3-nm Technology Node 亚- 3nm技术节点下水平堆叠硅纳米片场效应管优越的界面阱抗变异性
2021 International Semiconductor Conference (CAS) Pub Date : 2021-10-06 DOI: 10.1109/CAS52836.2021.9604183
A. Sudarsanan, O. Badami, K. Nayak
{"title":"Superior Interface Trap Variability Immunity of Horizontally Stacked Si Nanosheet FET in Sub-3-nm Technology Node","authors":"A. Sudarsanan, O. Badami, K. Nayak","doi":"10.1109/CAS52836.2021.9604183","DOIUrl":"https://doi.org/10.1109/CAS52836.2021.9604183","url":null,"abstract":"The effect of interface trap variability (ITV) on horizontally stacked nanosheet FET (NSHFET) has been explored using TCAD based 3-D quantum corrected Drift-Diffusion simulation framework for sub-3 nm technology node. It is revealed that 3-stacked NSHFET shows 9.09% lesser VT variation compared to 3-stacked nanowire FET (NWFET) due to combined ITV sources such as charge neutrality level (CNL), single charged traps (SCTs), and random interface traps (RITs). The 3-stacked NSHFET and NWFET reduces the ITV induced VT variation by 31.3% and 28.8% respectively compared to the single stacked transistors. The NSHFETs of higher effective channel width shows better immunity to ITV. It is found that both Si NSHFET and NWFET transistors effectively suppresses the combined ITV sources induced VT, ION, and drain induced barrier lowering (DIBL) variations when the CNL is positioned between midgap and conduction band edge of the semiconductor bandgap.","PeriodicalId":281480,"journal":{"name":"2021 International Semiconductor Conference (CAS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125279242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of DRAs for all-Silicon efficient millimeter-wave energy harvesters 全硅 高效毫米波能量采集器dra的设计
2021 International Semiconductor Conference (CAS) Pub Date : 2021-10-06 DOI: 10.1109/CAS52836.2021.9604175
S. Trovarello, D. Masotti, A. Costanzo
{"title":"Design of DRAs for all-Silicon efficient millimeter-wave energy harvesters","authors":"S. Trovarello, D. Masotti, A. Costanzo","doi":"10.1109/CAS52836.2021.9604175","DOIUrl":"https://doi.org/10.1109/CAS52836.2021.9604175","url":null,"abstract":"This paper presents the analysis and design of on-Silicon dielectric resonator antennas (DRAs) for energy harvesting applications. The proposed antennas, operating at 24 GHz and excited through a simple microstrip line, are built on a high-resistivity silicon substrate 0.525 mm-thick. The design of cylindrical and rectangular resonators using sapphire as dielectric material is first described, leading to 80% of maximum radiation efficiency and gain equal to 5.15 dBi. Given the increasing attention to system-on-a-chip (SoC) circuits, the second study proposed in this paper aims to a complete integrated solution, describing all-Silicon DRAs, both in cylindrical and rectangular shapes. Very promising performances are obtained in this case, too, from the twofold point of view of compactness and efficiency (75% radiation efficiency and gain equal to 4.72 dBi), if compared to standard solutions on Silicon. As a last step of the proposed study, an investigation on the miniaturization of DRAs operating at millimeter waves is described, exploiting high permittivity materials. In particular, a resonator with dielectric permittivity of 50, is analyzed.","PeriodicalId":281480,"journal":{"name":"2021 International Semiconductor Conference (CAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129231956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Tactile feedback through Velostat and motion algorithm for a neural prosthesis 基于Velostat和运动算法的神经假体触觉反馈
2021 International Semiconductor Conference (CAS) Pub Date : 2021-10-06 DOI: 10.1109/CAS52836.2021.9604201
Mirela-Iuliana Gheorghe, M. Dascalu, Florin Vasiliu, D. Dragomir, E. Franti
{"title":"Tactile feedback through Velostat and motion algorithm for a neural prosthesis","authors":"Mirela-Iuliana Gheorghe, M. Dascalu, Florin Vasiliu, D. Dragomir, E. Franti","doi":"10.1109/CAS52836.2021.9604201","DOIUrl":"https://doi.org/10.1109/CAS52836.2021.9604201","url":null,"abstract":"The objective of this paper is to find a solution for providing tactile feedback to a neural prosthesis prototype. Several sensors for contact and pressure were developed based on a sandwich-like structure with Velostat for getting a reaction from the prosthesis. An innovative motion algorithm, that uses the sensorial feed-back, was implemented: the \"Double Click\" command on a laptop touchpad. The signals received from the Velostat sensors presented in this paper can also be used for the stimulation of implanted electrodes, wrapped around the remaining nerves of the patients’ stump, and the user will perceive a tactile sensation. This way the bidirectional communication will be possible between the user and the prosthesis.","PeriodicalId":281480,"journal":{"name":"2021 International Semiconductor Conference (CAS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134241325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dark Current and Noise in Diffused and Epitaxial InAs Photodiodes 扩散和外延InAs光电二极管中的暗电流和噪声
2021 International Semiconductor Conference (CAS) Pub Date : 2021-10-06 DOI: 10.1109/CAS52836.2021.9604182
Tkachuk Andriy, Tetyorkin Volodymyr, Sukach Andriy
{"title":"Dark Current and Noise in Diffused and Epitaxial InAs Photodiodes","authors":"Tkachuk Andriy, Tetyorkin Volodymyr, Sukach Andriy","doi":"10.1109/CAS52836.2021.9604182","DOIUrl":"https://doi.org/10.1109/CAS52836.2021.9604182","url":null,"abstract":"A comparative analysis of the mechanisms of dark current and noise in InAs homo- and heterojunction photodiodes is carried out. It is shown that an excess current of a tunneling nature is the cause of the low-frequency 1/f noise at low temperatures. At high temperatures, the main source of noise is the generation-recombination current in the depleted area. Theoretical models of noise in infrared photodiodes are analyzed as applied to the experimental results obtained in this work.","PeriodicalId":281480,"journal":{"name":"2021 International Semiconductor Conference (CAS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134292750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Abnormal device performance in transferred multilayer MoS2 field-effect transistors 转移多层MoS2场效应晶体管的器件性能异常
2021 International Semiconductor Conference (CAS) Pub Date : 2021-10-06 DOI: 10.1109/CAS52836.2021.9604120
L. Tong, Jingyi Ma, Xinyu Chen, Xiaojiao Guo, Saifei Gou, Yingdong Xia, Die Wang, Honglei Chen, W. Bao
{"title":"Abnormal device performance in transferred multilayer MoS2 field-effect transistors","authors":"L. Tong, Jingyi Ma, Xinyu Chen, Xiaojiao Guo, Saifei Gou, Yingdong Xia, Die Wang, Honglei Chen, W. Bao","doi":"10.1109/CAS52836.2021.9604120","DOIUrl":"https://doi.org/10.1109/CAS52836.2021.9604120","url":null,"abstract":"Layered molybdenum disulfide (MoS2) is one of the representative two-dimensional (2D) semiconductors, offering a tantalizing prospect in the application of nanoelectronic devices and circuits. Here abnormal electrical and optoelectrical characteristics in transferred multilayer MoS2 transistors are observed and discussed. Such phenomena can be explained by the MoS2 intrinsic defects and the trapped charge impurities at the MoS2-dielectric and MoS2-MoS2 interfaces, as well as its charge screening effect. Our findings highlight the significance of controlling the dielectric interface and the material quality of 2D semiconductors, which are critical for the reliability of future 2D nanoelectronic devices.","PeriodicalId":281480,"journal":{"name":"2021 International Semiconductor Conference (CAS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134050386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Mechanism of Field-Plate Induced the Breakdown Voltage Change of High Voltage LDMOS 场极板诱导高压LDMOS击穿电压变化的机理
2021 International Semiconductor Conference (CAS) Pub Date : 2021-10-06 DOI: 10.1109/CAS52836.2021.9604135
Ching-Kuei Shih, Chih-Cherng Liao, K. Nidhi, Kai-Chuan Kan, Ke-Horng Chen, Jian-Hsing Lee
{"title":"The Mechanism of Field-Plate Induced the Breakdown Voltage Change of High Voltage LDMOS","authors":"Ching-Kuei Shih, Chih-Cherng Liao, K. Nidhi, Kai-Chuan Kan, Ke-Horng Chen, Jian-Hsing Lee","doi":"10.1109/CAS52836.2021.9604135","DOIUrl":"https://doi.org/10.1109/CAS52836.2021.9604135","url":null,"abstract":"The field-plate (FP) has been commonly used to increase the breakdown voltage for achieving the low on-resistance (Ron) high-voltage (HV) device. However, the mechanism of the FP induced the breakdown-voltage change of HV device is not fully understood. From the TCAD simulation, it finds that the electrical field of the reduced-surface field (RESURF) region of HV device is affected by the thickness differences of the dielectrics above this region. As the field-plate is inserted into these dielectrics, the dielectric thickness differences are reduced to lead to the electrical field suppression of RESURF region, resulting in the breakdown voltage increase of HV device.","PeriodicalId":281480,"journal":{"name":"2021 International Semiconductor Conference (CAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133441062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Wafer-level fabrication of nanocones structures by UV-nanoimprint and cryogenic deep reactive ion process 紫外-纳米压印和低温深度反应离子工艺制备纳米锥体结构
2021 International Semiconductor Conference (CAS) Pub Date : 2021-10-06 DOI: 10.1109/CAS52836.2021.9604179
O. Rasoga, C. Thanner, O. Semenova, A. Avram, Luiza-Izabela Jinga
{"title":"Wafer-level fabrication of nanocones structures by UV-nanoimprint and cryogenic deep reactive ion process","authors":"O. Rasoga, C. Thanner, O. Semenova, A. Avram, Luiza-Izabela Jinga","doi":"10.1109/CAS52836.2021.9604179","DOIUrl":"https://doi.org/10.1109/CAS52836.2021.9604179","url":null,"abstract":"UV-nanoimprint lithography is currently seen like an alternative to the classical lithographic techniques (electron beam or optical lithography) for large scale patterning in industrial applications. The present study is oriented on the fabrication of silicon nano-cones (pyramids) by using the UV-nanoimprint technique with polymeric stamps and deep reactive ion etching using the UV-cured resist as etching mask at cryogenic temperatures. The results show that the resist can act successfully as etching mask for the cryogenic silicon etching process.","PeriodicalId":281480,"journal":{"name":"2021 International Semiconductor Conference (CAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124489136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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