Superior Interface Trap Variability Immunity of Horizontally Stacked Si Nanosheet FET in Sub-3-nm Technology Node

Abstract

The effect of interface trap variability (ITV) on horizontally stacked nanosheet FET (NSHFET) has been explored using TCAD based 3-D quantum corrected Drift-Diffusion simulation framework for sub-3 nm technology node. It is revealed that 3-stacked NSHFET shows 9.09% lesser VT variation compared to 3-stacked nanowire FET (NWFET) due to combined ITV sources such as charge neutrality level (CNL), single charged traps (SCTs), and random interface traps (RITs). The 3-stacked NSHFET and NWFET reduces the ITV induced VT variation by 31.3% and 28.8% respectively compared to the single stacked transistors. The NSHFETs of higher effective channel width shows better immunity to ITV. It is found that both Si NSHFET and NWFET transistors effectively suppresses the combined ITV sources induced VT, ION, and drain induced barrier lowering (DIBL) variations when the CNL is positioned between midgap and conduction band edge of the semiconductor bandgap.