Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)最新文献_第2页

Package related reliability investigation with a multi-sensor chip 基于多传感器芯片的封装可靠性研究

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346817

R. van Gestel, L. van Gemert, E. Bagerman

引用次数: 2

High, performance optical data link array technology 高性能光数据链路阵列技术

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346758

R. A. Nordin, D. B. Buchholz, R. F. Huisman, N. Basavanhally, A. Levi

{"title":"High, performance optical data link array technology","authors":"R. A. Nordin, D. B. Buchholz, R. F. Huisman, N. Basavanhally, A. Levi","doi":"10.1109/ECTC.1993.346758","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346758","url":null,"abstract":"Demands for increased interconnection density and higher bandwidth, coupled with stringent cost constraints of advanced wide bandwidth telecommunication switching and high throughput computer architectures, are exhausting conventional electrical interconnection capabilities. The requirement for greater interconnection capabilities, spawned in part by the advances in integrated circuit technologies and the need for enhanced digital services, dictate that technology advancement must occur in traditional electronic packaging and/or interconnection techniques. The resolution of these technological needs is paramount for the successful competitive introduction of these systems. Presently, a \"bottle-neck\" occurs at the board-to-board level of the interconnection hierarchy, Therefore, an opportunity exists for the development of new parallel optical interconnection techniques which can be incorporated into system designs beginning at this interconnection level and beyond. The strategic insertion of parallel optical interconnection technology into these electronic processing systems not only meets projected performance requirements, but potentially offers them at a competitive cost.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128113449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Qualification testing of automotive terminals for high reliability applications 用于高可靠性应用的汽车接线端子的鉴定试验

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346850

P. Lees

{"title":"Qualification testing of automotive terminals for high reliability applications","authors":"P. Lees","doi":"10.1109/ECTC.1993.346850","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346850","url":null,"abstract":"The increasing sophistication of automotive electronic systems has presented some unique challenges to both the connector designer and the materials engineer. The automotive environment is abusive, yet reliability must be maintained over extended periods of time. For example, the life of safety related components must exceed the life of the vehicle. Automotive components are subjected to random vibration, thermal excursions, corrosive gasses, humidity and increasingly prolonged exposures to elevated temperatures. To determine the reliability of a connector design, comprehensive test specifications have evolved. A typical battery of tests includes, random vibration, temperature cycling with humidity, exposure to mixed flowing gas and thermal aging. This study examines the effect of contact finish on the performance of an automotive terminal. The contact finish was varied to explore cost reduction opportunities. The terminals were subjected to low cycle durability testing, temperature cycling with humidity, random vibration, and Battelle flowing mixed gas environments. System stability was evaluated in terms of low level circuit resistance changes. Test results are presented and the data indicate different responses depending on the contact finish properties. It was found that the performance of a thin, multi-layer clad inlay contact material met all test requirements and offered the lowest total system cost.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133961502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

New collimating lens systems for laser diode package 用于激光二极管封装的新型准直透镜系统

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346692

Y. Yagiu, T. Kumazawa, M. Shimaoka

引用次数: 2

Failure analysis mechanisms of miniaturized multilayer ceramic capacitors under normal service conditions 小型化多层陶瓷电容器在正常使用条件下的失效机理分析

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346689

Y. Chan, F. Yeung

引用次数: 6

Thermal and mechanical analysis of flip-chips on a liquid-cooled multichip module 液体冷却多芯片模块倒装芯片的热与力学分析

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346856

R. Narayanan, P. Hall, R. Chanchani

{"title":"Thermal and mechanical analysis of flip-chips on a liquid-cooled multichip module","authors":"R. Narayanan, P. Hall, R. Chanchani","doi":"10.1109/ECTC.1993.346856","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346856","url":null,"abstract":"In this paper, thermal analysis of a three dimensional quarter model of a 156 pad flip-chip on a liquid cooled multichip module with 75 other chips is simulated using COSMOS-finite element software. Both flip-chip (pad grid array type) and TAB type of interconnections are used for the module. The total power on the board is 134 watts, the flip-chips generating up to 1.5 watts each and the one TAB type generating 12 watts. Each chip can be modeled independently due to the absence of cross-heating by its neighbors. Forced convection liquid cooling using an organic coolant with various flow rates and thus various convection coefficients is used for the study. The temperature rise in the boundary layer of the coolant was 8/spl deg/F at the coolant flow rate of 0.073 gallons per minute for the flip-chip with 1.5 watts. The maximum thermal strains calculated were found to be 0.37% (if the temperature of zero strain is assumed to be 0/spl deg/F, and Young's modulus of solder is 2 Mpsi). The maximum shears were found in the corner bump, and they differed from the next bump by 20%. Polyimide layers above and below the solder bumps were found to contribute about 80% of the thermal resistance. These results are used in a Coffin-Manson analysis to predict adequate life (cycles) for the high lead solder bumps (95%Pb-5%Sn).<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114651414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Macromodels for generating signal integrity and timing management advice for package design 用于生成信号完整性和时序管理建议的宏模型

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346796

P. Franzon, S. Simovich, S. Mehrotra, M. Steer

引用次数: 8

A drawback of converting to a low stress molding compound 转换成低应力成型化合物的缺点

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346779

C. Virojanapa, M. Hadkeaw, D. Kane

引用次数: 0

High-density high-performance flexible cables for digital applications 用于数字应用的高密度高性能柔性电缆

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346781

A. Deutsch, G. Arjavalingam, C. Surovic, J. K. Tam, G. Kopcsay, D. W. Dranchak, J.B. Gillett

引用次数: 1

Feasibility study on through-wafer interconnecting method for hybrid wafer-scale-integration 混合晶圆规模集成的晶圆互连方法可行性研究

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI: 10.1109/ECTC.1993.346701

Y. Fujita, Y. Kawamura, K. Mizuishi

引用次数: 3