Package related reliability investigation with a multi-sensor chip

Abstract

To perform IC package related reliability research a test chip has been developed containing a large number of test structures. The structures are connected to multiplexing logic for performing electrical measurements. The chips have been used in a case study where PLCC 68 devices were stressed with a 500 Temperature Cycle Test and a 300 hours Highly Accelerated Stress Test. All the test structures are sensitive for open/short failures and were measured to monitor their behaviour. Acoustical scanning of the packages was used to measure die-surface delamination. The measurement of chip-package reliability is discussed in relation to the variance of the measurement results over the used chips in these reliability tests.<>