基于多传感器芯片的封装可靠性研究

Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93) Pub Date : 1993-06-01 DOI:10.1109/ECTC.1993.346817

R. van Gestel, L. van Gemert, E. Bagerman

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引用次数: 2

摘要

为了进行与集成电路封装相关的可靠性研究，开发了包含大量测试结构的测试芯片。该结构连接到多路复用逻辑，以执行电气测量。该芯片已在一个案例研究中使用，该案例研究中PLCC 68设备承受了500温度循环测试和300小时高加速压力测试。所有测试结构都对开/短失效敏感，并进行了测量以监测其行为。封装的声学扫描被用来测量模具表面分层。本文讨论了芯片封装可靠性的测量与这些可靠性测试中所用芯片的测量结果方差的关系。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Package related reliability investigation with a multi-sensor chip

To perform IC package related reliability research a test chip has been developed containing a large number of test structures. The structures are connected to multiplexing logic for performing electrical measurements. The chips have been used in a case study where PLCC 68 devices were stressed with a 500 Temperature Cycle Test and a 300 hours Highly Accelerated Stress Test. All the test structures are sensitive for open/short failures and were measured to monitor their behaviour. Acoustical scanning of the packages was used to measure die-surface delamination. The measurement of chip-package reliability is discussed in relation to the variance of the measurement results over the used chips in these reliability tests.<>

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Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)

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