{"title":"Novel manufacturing technology for microelectronic packaging fabrication","authors":"Y. Yau, M. Sarfaraz, N. S. Sandhu","doi":"10.1109/ECTC.1993.346838","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346838","url":null,"abstract":"Flexible, quick turn around and high density interconnection circuit patterning capabilities are key for packaging manufacturing as the industry grows at an increasingly competitive and faster pace. A novel fabrication technology for multilayer ceramic (MLC) packaging has been investigated and developed to meet these challenges. This flexible technology combines the data-driven high energy, high current electron beam technology with the unique integrated-mask (for thick film) metallization process technology to enable converting the circuit design data to fully metalized ceramic sheets in minutes. Thus, many different designs can be patterned and ready for stacking/lamination in days (i.e. no new punch heads or metallization masks needed). In addition, this technology will significantly reduce product development cycle time when utilized for product design verification and prototype build, significantly. This paper describes the novel packaging manufacturing technology and experimental results.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116850989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optical interconnects at the multi-chip module level; a view from the system level","authors":"D. H. Hartman","doi":"10.1109/ECTC.1993.346773","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346773","url":null,"abstract":"To the optical interconnect technologist, there exists a vision of implementation of the optical alternative at the multi-chip module (MCM) level. Expressed in its most basic form, the vision is that of a MCM being designed at a computer terminal wherein the designer has 10 or more layers of metal interconnect levels available,and perhaps 2 other layers, referred to as \"opto\" layers (optol, opto2). The opto layers consist of some electronically compatible dielectric layer that can be laid down and patterned to form very low-loss optical waveguides within the multi-layer MCM structure. These waveguides, and the associated driver/receiver electronics, have sufficiently superior optical performance characteristics and sufficiently robust mechanical/thermal properties that implementing them at the MCM level amounts to straightforward delineation of design rules for the layout engineer.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124800897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliability and thermal characterization of a 3-dimensional multichip module","authors":"A.W. Lin, A. Lyons, P. Simpkins","doi":"10.1109/ECTC.1993.346851","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346851","url":null,"abstract":"Three dimensional packaging extends the high interconnection density which has been achieved using multichip modules to a new dimension. In this paper, we describe the fabrication of an unique 3-dimensional multichip module (3-D MCM) based on AT&Ts Si-on-Si Micro Interconnect technology. Four multichip tiles are interconnected on a multilayer metal-core printing wiring board. Eight such boards are then stacked vertically to form a 3-D module. Compliant anisotropically conductive elastomers are the key element in this design providing electrical interconnection between the stacked boards. The heat generated by the multichip tiles is conducted to the metal-core board and removed by air forced through holes on the perimeter of the boards. This paper describes results of a reliability evaluation of the vertical interconnect scheme. In addition a thermal characterization of the 3-D module is presented.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128576150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Component reliability problems: their origins and manifestations","authors":"H. Chan","doi":"10.1109/ECTC.1993.346846","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346846","url":null,"abstract":"It is important to understand the root causes of component reliability problems and how they may systematically be diagnosed and eliminated using available test information. A generalized model is developed to show the relationship between where component reliability problems originate and where they are manifested. First, the model categorizes the components and their defects to distinguish their behavior toward different stress and test conditions. Hard defects are detectable with the right fault coverage but conditional or latent defects require certain applied stresses to show up. These differences in behavior will determine the effects of various processes on these components. Then, the processes in design, manufacture, testing and field-use are characterized as black-box operators that act on the component groupings. This model creates a clear linkage between where and how a component fails and the probable underlying cause of the failure. Such a global picture may then identify major areas to improve quality.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128208186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Lau, Y. Pao, C. Larner, R. Govila, S. Twerefour, D. Gilbert, S. Erasmus, S. Dolot
{"title":"Reliability of 0.4 mm pitch, 256-pin plastic quad flat pack no-clean and water-clean solder joints","authors":"J. Lau, Y. Pao, C. Larner, R. Govila, S. Twerefour, D. Gilbert, S. Erasmus, S. Dolot","doi":"10.1109/ECTC.1993.346854","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346854","url":null,"abstract":"The reliability of 0.4 mm pitch, 28 mm body size, 256-Pin Plastic Quad Flat Pack (QFP) no-clean and water-clean solder joints has been studied by temperature cycling and analytical analysis. The temperature cycling test was run non-stop for more than 6 months, and the results have been presented as a Weibull distribution. A unique temperature cycling profile has been developed based on the calculated lead stiffness, elastic and creep strains in the solder joint, and solder data. Also, the thermal fatigue life of the solder joints has been estimated and correlated with experimental results. Furthermore, a failure analysis of the solder joints has been performed using Scanning Electron Microscopy (SEM). Finally, a quantitative comparison between the no-clean and water-clean QFP solder joints has been presented.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128650986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Yamada, A. Tanaka, H. Shinohara, M. Honda, T. Hatada, A. Yamagiwa, Y. Shirai
{"title":"A CPU chip-on-board module","authors":"K. Yamada, A. Tanaka, H. Shinohara, M. Honda, T. Hatada, A. Yamagiwa, Y. Shirai","doi":"10.1109/ECTC.1993.346859","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346859","url":null,"abstract":"A CPU chip-on-board module for low and mid-range computers is described. The module consists of a CPU bare chip, 24 SRAMs packaged in the SOJ and some bypass capacitors. The module substrate is a printed circuit board (PCB) made of imide-triazine resin. The module (156 mm/spl times/58 mm) consists of four signal metal layers and four power/ground metal layers. A square through hole (17 mm/spl times/17 mm) for the CPU is formed in the central part of the PCB. A thermal spreading metal is glued to the PCB from the rear side, covering the square hole, and the CPU chip is die-bonded on the metal plate. The thermal resistance can be made smaller than 2/spl deg/C/W at a 0.4 m/s of wind velocity. Numerical analysis of electrical characteristics of the module shows that it can reduce signal delay time from the CPU to cache memories by 10% compared with that of a daughter board type module with the CPU packaged in a pin grid array. It is estimated that simultaneously switched noise can be reduced by 60% from that of the daughter board type module.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128759489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Flip-chip on FR-4 integrated circuit packaging","authors":"D. Powell, A. K. Trivedi","doi":"10.1109/ECTC.1993.346722","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346722","url":null,"abstract":"Technology advances have made it possible to extend the IBM C4 (Controlled Collapse Chip Connection) IC attachment method, also known as flip-chip, to printed circuit boards with low-cost dielectrics, such as FR-4. This new technology is referred to as Flip Chip Attach (FCA). In the past, C4 attachment had been limited to ceramic substrates due to the high temperature (360/spl deg/C) required to renew the low tin solder on the chips, and the need for the substrate to have its thermal expansion relatively closely matched to that of the silicon chip. The development of methods to deposit uniform, small (approximately 1/spl times/10/sup -3/ mm/sup 3/) volumes of eutectic tin/lead solder on printed circuit cards has allowed C4 bumped chips to be reflow soldered to the cards using standard SMT joining time/temperature profiles. The high melt (3-5% tin, balance lead) solder bump on the chip is used simply as a solder wettable device lead in this case. The resulting solder joint is not a true controlled collapse joint, but the process still maintains the self-aligning characteristic of C4, due to the surface tension of the molten eutectic solder and the low mass of the chip. The other enabling technology development for FCA is the use of a controlled expansion epoxy encapsulant between the chip and the substrate to minimize the cyclic strain on the solder joints induced by thermal expansion mismatch between the silicon chip and the FR-4 card. Without the use of such an encapsulant, the thermal cycle fatigue life of the FCA joints would be totally unacceptable, and the technology would be useless. In this paper we will explain how the enabling technologies work to make FCA a viable packaging method, and present reliability data for several different chips using FCA packaging.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121714130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The use of silver and silver plus gold conductors with the ferro low temperature tape","authors":"J. H. Alexander, A. Shaikh","doi":"10.1109/ECTC.1993.346747","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346747","url":null,"abstract":"For low temperature co-firable ceramic tape to play a significant role in the replacement of both alumina for high temperature packaging and conventional thick film hybrid materials on alumina it is essential that a full range of stable conductors, resistor and capacitor materials be available that are compatible with the LTCC during the firing process. The FERROTAPE A6 system provides for the first time such a range of materials to complement the unique properties of the tape, (low microwave insertion loss, K=5.9 and compatibility with silver conductors). The tape can be used with either silver or gold conductors and a technological breakthrough now allows both silver and gold to be used together as a result of the development of a novel via material. This paper presents information on the complete range of FERROTAPE A6 materials.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122939496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Coucoulas, A. Benzoni, M. F. Dautartas, R. Dutta, W. Holland, C. Nijander, R. Woods
{"title":"AlO bonding: a method of joining oxide optical components to aluminum coated substrates","authors":"A. Coucoulas, A. Benzoni, M. F. Dautartas, R. Dutta, W. Holland, C. Nijander, R. Woods","doi":"10.1109/ECTC.1993.346803","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346803","url":null,"abstract":"With the increased use of photonic packages, there are needs for reliable and low cost methods of attaching optical components. Packages based on silicon optical bench (SiOB) technology include oxide coated ball-lenses and silica fibers which are generally epoxied in anisotropically etched features of silicon substrates. The reliable attachment of these micro-optical components requires the application of small (approximately 1 nanoliter) quantities of epoxy at precise locations on the substrate. This is a time consuming process and requires considerable operator training and skill. Dispensing too much epoxy can deteriorate the optical performance of the device and dispensing too little results in an insufficient holding power. AlO bonding is an alternative attachment technique, under development, which forms solid-state bonds directly between these oxide-components and aluminum thin film coated silicon optical bench substrates and therefore does not require the handling of additives, such as epoxy, at the bond interface. This paper includes: methods of bonding ball-lenses and fibers; an interfacial analysis and proposed bonding mechanism derived from SEM/metallographic photomicrographs and thermodynamic data; destructive test results as a function of bonding and material parameters and; in situ loss measurements through AlO bonded components (multi-, single mode fibers and ball-lenses) during the bonding procedures and subsequent thermal cycling (-40 to 80/spl deg/C and from ambient to -195.8/spl deg/C) tests.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122959773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High K thick film and tape material","authors":"D.H. Dychala, P. Bless, R.L. Wahlers, S. Stein","doi":"10.1109/ECTC.1993.346748","DOIUrl":"https://doi.org/10.1109/ECTC.1993.346748","url":null,"abstract":"A new series of capacitor materials with dielectric constants approaching 14,000 has been developed. These materials were formulated into both thick film and cofire tape formats and are compatible with Ag, Pt/Ag and Au conductors. Optimum firing range is 900-930/spl deg/C. New low fire vitreous overglazes provide the thick film capacitors with environmental reliability and stability.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"687 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123054021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}