K. Yamada, A. Tanaka, H. Shinohara, M. Honda, T. Hatada, A. Yamagiwa, Y. Shirai
{"title":"A CPU chip-on-board module","authors":"K. Yamada, A. Tanaka, H. Shinohara, M. Honda, T. Hatada, A. Yamagiwa, Y. Shirai","doi":"10.1109/ECTC.1993.346859","DOIUrl":null,"url":null,"abstract":"A CPU chip-on-board module for low and mid-range computers is described. The module consists of a CPU bare chip, 24 SRAMs packaged in the SOJ and some bypass capacitors. The module substrate is a printed circuit board (PCB) made of imide-triazine resin. The module (156 mm/spl times/58 mm) consists of four signal metal layers and four power/ground metal layers. A square through hole (17 mm/spl times/17 mm) for the CPU is formed in the central part of the PCB. A thermal spreading metal is glued to the PCB from the rear side, covering the square hole, and the CPU chip is die-bonded on the metal plate. The thermal resistance can be made smaller than 2/spl deg/C/W at a 0.4 m/s of wind velocity. Numerical analysis of electrical characteristics of the module shows that it can reduce signal delay time from the CPU to cache memories by 10% compared with that of a daughter board type module with the CPU packaged in a pin grid array. It is estimated that simultaneously switched noise can be reduced by 60% from that of the daughter board type module.<<ETX>>","PeriodicalId":281423,"journal":{"name":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE 43rd Electronic Components and Technology Conference (ECTC '93)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.1993.346859","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A CPU chip-on-board module for low and mid-range computers is described. The module consists of a CPU bare chip, 24 SRAMs packaged in the SOJ and some bypass capacitors. The module substrate is a printed circuit board (PCB) made of imide-triazine resin. The module (156 mm/spl times/58 mm) consists of four signal metal layers and four power/ground metal layers. A square through hole (17 mm/spl times/17 mm) for the CPU is formed in the central part of the PCB. A thermal spreading metal is glued to the PCB from the rear side, covering the square hole, and the CPU chip is die-bonded on the metal plate. The thermal resistance can be made smaller than 2/spl deg/C/W at a 0.4 m/s of wind velocity. Numerical analysis of electrical characteristics of the module shows that it can reduce signal delay time from the CPU to cache memories by 10% compared with that of a daughter board type module with the CPU packaged in a pin grid array. It is estimated that simultaneously switched noise can be reduced by 60% from that of the daughter board type module.<>