2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)最新文献

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A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform 低功耗异构SoC平台51mW 1.6GHz片上网络
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332639
Kangmin Lee, Se-Joong Lee, Sung-Eun Kim, Hye-Mi Choi, Donghyun Kim, Sunyoung Kim, Min-wuk Lee, H. Yoo
{"title":"A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform","authors":"Kangmin Lee, Se-Joong Lee, Sung-Eun Kim, Hye-Mi Choi, Donghyun Kim, Sunyoung Kim, Min-wuk Lee, H. Yoo","doi":"10.1109/ISSCC.2004.1332639","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332639","url":null,"abstract":"A 1.6GHz on-chip network integrating two processors, memories, and an FPGA provides 11.2GB/s bandwidth in 0.18/spl mu/m 6M CMOS technology. The 2-level hierarchical star-connected network using serialized low-energy transmission coding, crossbar partial activation and lowswing signaling dissipates 51 mW at 1.6V supporting globally asynchronous, locally synchronous mode and programmable clocking.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125113191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 104
Emerging technology and business solutions for system chips 系统芯片的新兴技术和业务解决方案
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332580
N. Lu
{"title":"Emerging technology and business solutions for system chips","authors":"N. Lu","doi":"10.1109/ISSCC.2004.1332580","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332580","url":null,"abstract":"In three decades, the IC industry grew from nothing to current GSI levels (with 10/sup 9/ devices on a chip). Its major driving force has been the use of device scaling, which has been especially effective in enhancing the performance of digital chips. However, increasingly, diverse system applications have created an additional driving force - the development of more and more system chips with an increased need to integrate more diverse functionality (digital, analog, memory, RF, etc.) within a limited form factor. In addition to current SoCs on a 2D die, a trend for the coming decade is multidimensional die integration on interconnected substrates in a compact package. Correspondingly, a metric analyzing technology trends is presented. At the same time, beyond the innovative foundry/fabless business structure of the 1990s, new business models are evolving for the realization of system chips. Such models, leading to an effective solution called virtual vertical integration, is discussed. System-chip development must also be vertically integrated to achieve optimized performance, but advanced technologies required to realize such integration cover various horizontal segments of knowledge, such as multidimensional-die architecture design, circuit design, and related design automation, as well as novel testing and packaging techniques, leading-edge device and wafer-fabrication technologies, and solution-oriented software coding. In this regard, critical challenges are highlighted in terms of power partitioning, integrated design, and built-in quality assurance for known-good-die, signal integrity in field applications, and technology optimization across different segments. The parallelism of technology solutions with business models, and their conjoined optimization in the coming system-chip era, is illustrated in this paper.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127641222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications 3V CMOS 400mW 14b 1.4GS/s DAC多载波应用
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332743
Bernd Schafferer, R. Adams
{"title":"A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications","authors":"Bernd Schafferer, R. Adams","doi":"10.1109/ISSCC.2004.1332743","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332743","url":null,"abstract":"This paper presents an uncalibrated 0.18 /spl mu/m CMOS 14 bit 1.4 GS/s DAC, with an LVDS interface, which achieves 67 dB SFDR for a 260 MHz full-scale tone and 70 dB ACLR for a two-carrier output, centered at 470 MHz. The IC dissipates a core power of 200 mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132619838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 105
/spl Sigma//spl Delta/ ADC with finite impulse response feedback DAC /spl Sigma//spl Delta/ ADC,具有有限脉冲响应反馈DAC
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332601
Bas M. Putter
{"title":"/spl Sigma//spl Delta/ ADC with finite impulse response feedback DAC","authors":"Bas M. Putter","doi":"10.1109/ISSCC.2004.1332601","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332601","url":null,"abstract":"A continuous-time 1 b /spl Sigma//spl Delta/ ADC with a finite impulse response DAC in the feedback path is presented. The FIRDAC reduces the susceptibility to clock jitter by 18 dB while maintaining linearity. S/N ratio is 77 dB in a 1 MHz bandwidth, and IM2 and IM3 are 77 dB and 82 dB, respectively. The 0.18 /spl mu/m CMOS chip consumes 6.0 mW.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133580446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
A zero-sink-current Schmitt trigger and window-flexible counting circuit for fingerprint sensor/identifier 用于指纹传感器/识别器的零沉电流施密特触发和窗口柔性计数电路
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332624
H. Morimura, T. Shimannura, K. Fujii, S. Shigematsu, Y. Okazaki, M. Katsuyuki
{"title":"A zero-sink-current Schmitt trigger and window-flexible counting circuit for fingerprint sensor/identifier","authors":"H. Morimura, T. Shimannura, K. Fujii, S. Shigematsu, Y. Okazaki, M. Katsuyuki","doi":"10.1109/ISSCC.2004.1332624","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332624","url":null,"abstract":"Pixel-parallel architecture with 1b ADC per pixel achieves 6.4/spl mu/W dissipation. Pixel memory element and event counting sensing circuitry control fingerprint acquisition. A 224 x 256 pixel array is built in a 0.25/spl mu/m CMOS process.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131086142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Reconfigurable RF circuits based on integrated MEMS switches 基于集成MEMS开关的可重构射频电路
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332718
J. DeNatale
{"title":"Reconfigurable RF circuits based on integrated MEMS switches","authors":"J. DeNatale","doi":"10.1109/ISSCC.2004.1332718","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332718","url":null,"abstract":"MEMS phase shifters, based on switchable passive components, are used to achieve a variety of circuits with low insertion loss, wide bandwidth and compact die size. Integration of MEMS switches with active GaAs pHEMT MMICs achieves reconfigurable LNA and PA devices. A 4 b true time-delay phase-shifter achieves /spl les/1.2 dB insertion loss on a 7 mm/sup 2/ die.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128208410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 2GS/s 3b /spl Delta//spl Sigma/-modulated DAC with a tunable switched-capacitor bandpass DAC mismatch shaper 2GS/s 3b /spl Delta//spl Sigma/调制DAC,带可调开关电容带通DAC失配整形器
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332746
T. Kaplan, J. Jensen, C. Fields, M. Chang
{"title":"A 2GS/s 3b /spl Delta//spl Sigma/-modulated DAC with a tunable switched-capacitor bandpass DAC mismatch shaper","authors":"T. Kaplan, J. Jensen, C. Fields, M. Chang","doi":"10.1109/ISSCC.2004.1332746","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332746","url":null,"abstract":"A 3b /spl Delta//spl Sigma/-modulated mismatch-shaped DAC is presented. The mismatch shaper uses 7 tunable 1.5b switched-capacitor bandpass /spl Delta//spl Sigma/ modulators to dynamically route the digital signals to the DACs. The DAC can generate narrowband signals from 250 to 750MHz with /spl ges/68dB SNR, /spl ges/74dB SFDR, and -80dBc intermodulation distortion.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133007634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low-voltage-swing logic circuits for a 7GHz x86 integer core 用于7GHz x86整数内核的低压摆幅逻辑电路
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332640
D. Deleganes, M. Barany, G. Geannopoulos, K. Kreitzer, A.P. Singh, S. Wijeratne
{"title":"Low-voltage-swing logic circuits for a 7GHz x86 integer core","authors":"D. Deleganes, M. Barany, G. Geannopoulos, K. Kreitzer, A.P. Singh, S. Wijeratne","doi":"10.1109/ISSCC.2004.1332640","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332640","url":null,"abstract":"Pentium/spl reg/4 processor architecture uses a 2x core clock to implement low latency integer operations. Low-voltage-swing logic circuits in 90nm technology meet the frequency demands of a 3rd generation integer core, with operation demonstrated for frequencies in excess of 7GHz.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133217506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
VSWR-protected silicon bipolar power amplifier with smooth power control slope 具有平滑功率控制斜率的vswr保护硅双极功率放大器
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332660
A. Scuderi, F. Carrara, G. Palmisano
{"title":"VSWR-protected silicon bipolar power amplifier with smooth power control slope","authors":"A. Scuderi, F. Carrara, G. Palmisano","doi":"10.1109/ISSCC.2004.1332660","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332660","url":null,"abstract":"A 1.8 GHz silicon bipolar PA is presented. A protection circuit enables the amplifier to sustain a 10:1 load VSWR at 5 V supply despite a low BV/sub ceo/ of 6.5 V. A temperature-compensated bias network allows a moderate power-control slope of less than 80 dB/V. A 50% PAE is attained at a 33.8 dBm output power level. The 1.2/spl times/1.5 mm/sup 2/ die is implemented in 0.8 /spl mu/m BiPMOS.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133406050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Architecture and circuit techniques for a reconfigurable memory block 可重构存储器块的结构和电路技术
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI: 10.1109/ISSCC.2004.1332813
K. Mai, R. Ho, E. Alon, L. Dean, Younggon Kim, P. Dinesh, M. Horowitz
{"title":"Architecture and circuit techniques for a reconfigurable memory block","authors":"K. Mai, R. Ho, E. Alon, L. Dean, Younggon Kim, P. Dinesh, M. Horowitz","doi":"10.1109/ISSCC.2004.1332813","DOIUrl":"https://doi.org/10.1109/ISSCC.2004.1332813","url":null,"abstract":"A 2 kB reconfigurable SRAM block, using self-timed, pulse-mode circuits capable of emulating a portion of a cache or a streaming FIFO is realized in a 1.8 V 0.18 /spl mu/m CMOS process and operates at 1.1 GHz (10F04 cycle). The additional logic needed for reconfigurability consumes 26% of the total power and 32% of the total area.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128832623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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