可重构存储器块的结构和电路技术

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332813

K. Mai, R. Ho, E. Alon, L. Dean, Younggon Kim, P. Dinesh, M. Horowitz

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引用次数: 18

摘要

在1.8 V 0.18 /spl mu/m CMOS工艺中实现了一个2kb可重构SRAM块，使用自定时脉冲模式电路，能够模拟部分缓存或流FIFO，工作频率为1.1 GHz (10F04周期)。可重构性所需的额外逻辑消耗了总功率的26%和总面积的32%。

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Architecture and circuit techniques for a reconfigurable memory block

A 2 kB reconfigurable SRAM block, using self-timed, pulse-mode circuits capable of emulating a portion of a cache or a streaming FIFO is realized in a 1.8 V 0.18 /spl mu/m CMOS process and operates at 1.1 GHz (10F04 cycle). The additional logic needed for reconfigurability consumes 26% of the total power and 32% of the total area.

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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