用于7GHz x86整数内核的低压摆幅逻辑电路

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332640

D. Deleganes, M. Barany, G. Geannopoulos, K. Kreitzer, A.P. Singh, S. Wijeratne

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引用次数: 21

摘要

Pentium/spl reg/4处理器架构采用2核时钟实现低延迟整数运算。90nm技术的低压摆动逻辑电路满足第三代整数核心的频率需求，并演示了在超过7GHz频率下的操作。

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Low-voltage-swing logic circuits for a 7GHz x86 integer core

Pentium/spl reg/4 processor architecture uses a 2x core clock to implement low latency integer operations. Low-voltage-swing logic circuits in 90nm technology meet the frequency demands of a 3rd generation integer core, with operation demonstrated for frequencies in excess of 7GHz.

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来源期刊

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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