D. Deleganes, M. Barany, G. Geannopoulos, K. Kreitzer, A.P. Singh, S. Wijeratne
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引用次数: 21
Abstract
Pentium/spl reg/4 processor architecture uses a 2x core clock to implement low latency integer operations. Low-voltage-swing logic circuits in 90nm technology meet the frequency demands of a 3rd generation integer core, with operation demonstrated for frequencies in excess of 7GHz.